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preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 2002 (all rights reserved) p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.cirrus.com cs61880 octal e1 line interface unit features ? octal e1 short-haul line interface unit ? low power ? no external component changes for 120 ? / 75 ? operation ? pulse shapes can be customized by the user ? internal ami, or hdb3 encoding/decoding ? los detection per itu g.775 or etsi 300- 233 ? g.772 non-intrusive monitoring ? g.703 bits clock recovery ? crystal-less jitter attenuation ? serial/parallel microprocessor control interfaces ? transmitter short circuit current limiter (<50 ma) ? tx drivers with fast high-z and power down ? jtag boundary scan compliant to ieee 1149.1 ? 144-pin lqfp or 160-pin fbga package ordering information cs61880-iq 144-pin lqfp cs61880-ib 160-pin fbga description the cs61880 is a full-featured octal e1 short-haul liu that supports 2.048 mbps data transmission for both e1 75 ? and e1 120 ? applications. each channel provides crystal-less jitter attenuation that complies with the most stringent standards. each channel also provides internal ami/hdb3 encoding/decoding. to support enhanced system diagnostics, channel zero can be configured for g.772 non-intrusive monitoring of any of the other 7 channels? receive or transmit paths. the cs61880 makes use of ultra low power matched im- pedance transmitters and receivers to reduce power beyond that achieved by traditional driver designs. by achieving a more precise line match, this technique also provides superior return loss characteristics. additional- ly, the internal line matching circuitry reduces the external component count. all transmitters have controls for independent power down and high-z. each receiver provides reliable data recovery with over 12 db of cable attenuation. the receiver also incorpo- rates los detection compliant to the most recent specifications. rpos rneg tpos tneg tclk los rtip rring ttip tring rclk 0 1 7 jtag interface remote loopback digital loopback analog loopback decoder driver receiver los g.772 monitor transmit control pulse shaper data recovery jitter attenuator clock recovery encoder host interface jtag serial port host serial/parallel port aug ?02 ds450pp2
cs61880 2 ds450pp2 table of contents 1. pin out - 144-pin lqfp package ...................................................................................... 7 2. pin out - 160-ball fbga package .................................................................................. 8 3. pin descriptions .......................................................................................................... ...... 9 3.1 power supplies ............................................................................................................ ...... 9 3.2 control ................................................................................................................... .......... 10 3.3 address inputs/loopbacks ............................................................................................... 14 3.4 cable select .............................................................................................................. ...... 15 3.5 status .................................................................................................................... ........... 15 3.6 digital rx/tx data i/o .................................................................................................... .. 16 3.7 analog rx/tx data i/o .................................................................................................... 1 9 3.8 jtag test interface ....................................................................................................... .. 21 3.9 miscellaneous ............................................................................................................. ..... 21 4. operation ................................................................................................................. .......... 22 5. power-up .................................................................................................................. ........... 22 6. master clock .............................................................................................................. ..... 22 7. g.772 monitoring .......................................................................................................... .... 22 8. building integrated timing systems (bits) clock mode .................................. 23 9. transmitter ............................................................................................................... ........ 24 9.1 bipolar mode .............................................................................................................. ...... 24 9.2 unipolar mode ............................................................................................................. ..... 24 9.3 rz mode ................................................................................................................... ....... 25 9.4 transmitter powerdown / high-z ..................................................................................... 25 9.5 transmit all ones (taos) ............................................................................................... 25 9.6 automatic taos ............................................................................................................ .. 25 9.7 driver failure monitor .................................................................................................... .. 25 9.8 driver short circuit protection ......................................................................................... 25 10. receiver ................................................................................................................. ........... 26 10.1 bipolar output mode ...................................................................................................... 26 10.2 unipolar output mode .................................................................................................... 2 6 10.3 rz output mode ........................................................................................................... .26 10.4 receiver powerdown/high-z ......................................................................................... 27 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm important notice ?preliminary? product information describes products that are in production, but for which full characterization data is not ye t available. ?advance? product infor- mation describes products that are in development and subject to development changes. cirrus logic, inc. and its subsidiaries ( ?cirrus?) believe that the infor- mation contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of or der acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liab ility. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, copyright s, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other parts of cirrus. this consent does not ext end to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. an export permit needs to be obtained from the competent authorities of the japanese government if any of the products or techn ologies described in this ma- terial and controlled under the ?foreign exchange and foreign trade law? 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cs61880 ds450pp2 3 10.5 loss-of-signal (los) ..................................................................................................... 27 10.6 alarm indication signal (ais) ......................................................................................... 27 11. jitter attenuator ........................................................................................................ 28 12. operational summary ................................................................................................ 29 12.1 loopbacks ................................................................................................................ ..... 29 12.2 analog loopback .......................................................................................................... .29 12.3 digital loopback ......................................................................................................... ... 30 12.4 remote loopback ......................................................................................................... 3 0 13. host mode ................................................................................................................ ........ 32 13.1 software reset ..................................................................................................... 32 13.2 serial port operation .................................................................................................... .32 13.3 parallel port operation .................................................................................................. 33 13.4 register set ............................................................................................................. ...... 34 14. register descriptions ................................................................................................ 35 14.1 revision/idcode register (00h) ..................................................................................... 35 14.2 analog loopback register (01h) ................................................................................... 35 14.3 remote loopback register (02h) .................................................................................. 35 14.4 taos enable register (03h) ......................................................................................... 35 14.5 los status register (04h) ............................................................................................ 35 14.6 dfm status register (05h) ............................................................................................ 35 14.7 los interrupt enable register (06h) ............................................................................. 36 14.8 dfm interrupt enable register (07h) ............................................................................ 36 14.9 los interrupt status register (08h) .............................................................................. 36 14.10 dfm interrupt status register (09h) ........................................................................... 36 14.11 software reset register (0ah) .................................................................................... 36 14.12 performance monitor register (0bh) ........................................................................... 36 14.13 digital loopback reset register (0ch) ....................................................................... 36 14.14 los/ais mode enable register (0dh) ........................................................................ 37 14.15 automatic taos register (0eh) .................................................................................. 37 14.16 global control register (0fh) ...................................................................................... 37 14.17 line length channel id register (10h) ....................................................................... 38 14.18 line length data register (11h) ................................................................................. 38 14.19 output disable register (12h) ..................................................................................... 38 14.20 ais status register (13h) ............................................................................................ 38 14.21 ais interrupt enable register (14h) ............................................................................ 39 14.22 ais interrupt status register (15h) ............................................................................. 39 14.23 awg broadcast register (16h) ................................................................................... 39 14.24 awg phase address register (17h) ........................................................................... 39 14.25 awg phase data register (18h) ................................................................................ 39 14.26 awg enable register (19h) ........................................................................................ 40 14.27 awg overflow interrupt enable register (1ah) .......................................................... 40 14.28 awg overflow interrupt status register (1bh) ........................................................... 40 14.29 reserved register (1ch) ............................................................................................. 40 14.30 reserved register (1dh) ............................................................................................. 40 14.31 bits clock enable register (1eh) ................................................................................ 40 14.32 reserved register (1fh) ............................................................................................. 40 14.33 status registers ........................................................................................................ .. 41 14.33.1 interrupt enable registers .............................................................................. 41 14.33.2 interrupt status registers ............................................................................... 41 15. arbitrary waveform generator ........................................................................... 42 16. jtag support ............................................................................................................. ..... 43 16.1 tap controller ........................................................................................................... .... 44 16.1.1 jtag reset ...................................................................................................... 44
cs61880 4 ds450pp2 16.1.2 test-logic-reset ............................................................................................... 44 16.1.3 run-test-idle .................................................................................................... 44 16.1.4 select-dr-scan ................................................................................................ 44 16.1.5 capture-dr ....................................................................................................... 44 16.1.6 shift-dr ............................................................................................................. 44 16.1.7 exit1-dr ............................................................................................................ 44 16.1.8 pause-dr .......................................................................................................... 45 16.1.9 exit2-dr ............................................................................................................ 45 16.1.10 update-dr ...................................................................................................... 45 16.1.11 select-ir-scan ................................................................................................ 45 16.1.12 capture-ir ....................................................................................................... 45 16.1.13 shift-ir ............................................................................................................ 45 16.1.14 exit1-ir ........................................................................................................... 46 16.1.15 pause-ir ......................................................................................................... 46 16.1.16 exit2-ir ........................................................................................................... 46 16.1.17 update-ir ........................................................................................................ 46 16.2 instruction register (ir) ................................................................................................ .46 16.2.1 extest ............................................................................................................ 46 16.2.2 sample/preload ......................................................................................... 46 16.2.3 idcode ............................................................................................................ 46 16.2.4 bypass ............................................................................................................ 46 16.3 device id register (idr) ............................................................................................... 47 17. boundary scan register (bsr) ................................................................................ 47 18. applications ............................................................................................................. ....... 50 18.1 transformer specifications ............................................................................................ 52 18.2 crystal oscillator specifications ..................................................................................... 52 18.3 line protection .......................................................................................................... ..... 52 19. characteristics and specifications .................................................................... 53 19.1 absolute maximum ratings ........................................................................................... 53 19.2 recommended operating conditions ............................................................................ 53 19.3 digital characteristics .................................................................................................. .. 54 19.4 transmitter analog characteristics ................................................................................ 54 19.5 receiver analog characteristics .................................................................................... 55 19.6 jitter attenuator characteristics ..................................................................................... 56 19.7 master clock switching characteristics ......................................................................... 58 19.8 transmit switching characteristics ................................................................................ 58 19.9 receive switching characteristics ................................................................................. 58 19.10 switching characteristics - serial port ......................................................................... 60 19.11 switching characteristics - parallel port (multiplexed mode) ..................................... 61 19.12 switching characteristics- parallel port (non-multiplexed mode) ............................... 64 19.13 switching characteristics - jtag ................................................................................ 67 20. compliant recommendations and specifications .......................................... 68 21. 160-ball fbga package dimensions ........................................................................ 69 22. 144-pin lqfp package dimensions ....................................................................... 70
cs61880 ds450pp2 5 list of figures figure 1. cs61880 144-pin lqfp package pin outs .................................................................... 7 figure 2. cs61880 160-ball fbga package pin outs ................................................................... 8 figure 3. g.703 bits clock mode in nrz mode .......................................................................... 23 figure 4. g.703 bits clock mode in rz mode............................................................................. 23 figure 5. g.703 bits clock mode in remote loopback .............................................................. 23 figure 6. pulse mask at e1 interface .......................................................................................... .24 figure 7. analog loopback block diagram................................................................................... 30 figure 8. analog loopback with taos block diagram................................................................. 30 figure 9. digital loopback block diagram .................................................................................... 31 figure 10. digital loopback with taos ........................................................................................ 31 figure 11. remote loopback block diagram ............................................................................... 31 figure 12. serial read/write format (spol = 0) ......................................................................... 33 figure 13. arbitrary waveform ui ............................................................................................... .. 42 figure 14. test access port architecture...................................................................................... 4 4 figure 15. tap controller state diagram ..................................................................................... 45 figure 16. internal rx/tx impedance matching ........................................................................... 50 figure 17. internal tx, external rx impedance matching............................................................ 51 figure 18. jitter transfer characteristic vs. g.736 & tbr 12/13.................................................. 56 figure 19. jitter tolerance characteristic vs. g.823..................................................................... 57 figure 20. recovered clock and data switching characteristics................................................. 59 figure 21. transmit clock and data switching characteristics .................................................... 59 figure 22. signal rise and fall characteristics ............................................................................ 59 figure 23. serial port read timing diagram ................................................................................ 60 figure 24. serial port write timing diagram ................................................................................ 60 figure 25. parallel port timing - write; intel multiplexed address / data bus mode .................... 62 figure 27. parallel mode port timing - read; intel multiplexed address / data bus mode......... 62 figure 26. parallel port timing - write; motorola multiplexed address / data bus mode............. 63 figure 28. parallel port timing - read; motorola multiplexed address / data bus mode............. 63 figure 29. parallel port timing - read; intel non-multiplexed address / data bus mode ............ 65 figure 30. parallel port timing - write; intel non-multiplexed address / data bus mode ............ 65 figure 31. parallel port timing - read; motorola non-multiplexed address / data bus mode..... 66 figure 32. parallel port timing - write; motorola non-multiplexed address / data bus mode ..... 66 figure 33. jtag switching characteristics................................................................................... 67 figure 34. 160-ball fbga package drawing................................................................................ 69 figure 35. 144-pin lqfp package drawing ................................................................................. 70
cs61880 6 ds450pp2 list of tables table 1. operation mode selection .............................................................................................. ....... 10 table 2. mux/bits clock selection .............................................................................................. ......... 11 table 3. jitter attenuation selection .......................................................................................... .......... 12 table 4. cable impedance selection ............................................................................................. ...... 15 table 5. bipolar mode translations ............................................................................................. ........ 16 table 6. g.772 address selection ............................................................................................... ........ 22 table 7. jitter attenuator configurations ...................................................................................... ....... 28 table 8. operational summary ................................................................................................... ......... 29 table 9. host control signal descriptions ...................................................................................... ..... 32 table 10. host mode register set............................................................................................... ........ 34 table 11. jitter attenuator position selection ................................................................................. ..... 37 table 12. transmitter pulse shape selection .................................................................................... .38 table 13. jtag instructions .................................................................................................... ............ 46 table 14. boundary scan register ............................................................................................... ....... 47 table 15. transformer specifications ........................................................................................... ....... 52 table 16. 144-pin package dimensions........................................................................................... ... 70
cs61880 ds450pp2 7 1. pin out - 144-pin lqfp package 144 143 142 140 139 138 137 136 135 141 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 cs61880 144-pin lqfp 37 38 39 41 42 43 44 45 46 40 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 104 103 102 101 100 99 105 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 119 118 117 116 115 114 113 112 111 110 109 1 2 3 5 6 7 8 9 10 4 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 tneg7/ubs7 rclk7 rpos7/rdata7 rneg7/bpv7 los7 rtip7 rring7 tv+7 ttip7 tring7 tgnd7 rring6 rtip6 tgnd6 tring6 ttip6 tv+6 rtip5 rring5 tv+5 ttip5 tring5 tgnd5 rring4 rtip4 tgnd4 tring4 ttip4 tv+4 clke txoe los4 rneg4/bpv4 rpos4/rdata4 rclk4 tneg4/ubs4 tpos7/tdata7 tclk7 los6 rneg6/bpv6 rpos6/rdata6 rclk6 tneg6/ubs6 tpos6/tdata6 tclk6 mclk mode a4 a3 a2 a1 a0 vccio gndio rv0+ rgnd0 loop0/d0 loop1/d1 loop2/d2 loop3/d3 loop4/d4 loop5/d5 loop6/d6 loop7/d7 tclk1 tpos1/tdata1 tneg1/ubs1 rclk1 rpos1/rdata1 rneg1/bpv1 los1 tclk0 tpos0/tdata0 tneg0/usb0 rclk0 rpos0/rdata0 rneg0/bpv0 los0 mux/bitsen0 tv+0 ttip0 tring0 tgnd0 rtip0 rring0 tgnd1 tring1 ttip1 tv+1 rring1 rtip1 tv+2 ttip2 tring2 tgnd2 rtip2 rring2 tgnd3 tring3 ttip3 tv+3 rring3 rtip3 los3 rneg3/rbpv3 rpos3/rdata3 rclk3 tneg3/ubs3 (top view) tpos4/tdata4 tclk4 los5 rneg5/bpv5 rpos5/rdata5 rclk5 tneg5/ubs5 tpos5/tdata5 tclk5 tdi tdo tck tms trst ref cblsel vccio gndio rv1+ rgnd1 intl/mot/coden cs/jasel ale/as/sclk rd/rw wr/ds/sdi rdy/ack/sdo int tclk2 tpos2/tdata2 tneg2/ubs2 rclk2 rpos2/rdata2 rneg2/bpv2 los2 tclk3 tpos3/tdata3 figure 1. cs61880 144-pin lqfp package pin outs
cs61880 8 ds450pp2 2. pin out - 160-ball fbga package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 clke tdo cblsel ref tpos 5 rpos 4 tpos 4 rpos 5 tpos 2 rpos 3 tpos 3 rpos 2 ttip 5 tring 4 ttip 4 tring 5 ttip 2 tring 3 ttip 3 tring 2 tgnd 5 tgnd 4 tgnd 4 tgnd 5 tgnd 2 tgnd 3 tgnd 3 tgnd 2 rring 5 rtip 4 rring 4 rtip 5 rring 2 rtip 3 rring 3 rtip 2 rring 6 rtip 7 rring 7 rtip 6 rring 1 rtip 0 rring 0 rtip 1 tgnd 6 tgnd 7 tgnd 7 tgnd 6 tgnd 1 tgnd 0 tgnd 0 tgnd 1 ttip 6 tring 7 ttip 7 tring 6 ttip 1 tring 0 ttip 0 tring 1 tvcc 6 tvcc 7 tvcc 7 tvcc 6 tvcc 1 tvcc 0 tvcc 0 tvcc 1 los 7 a4 gndio loop 3 los 0 rgnd 0 tneg 6 rneg 7 tneg 7 rneg 6 tneg 1 rneg 0 tneg 0 rneg 1 los 6 a3 a0 loop 4 los 1 loop 1 tpos 6 rpos 7 tpos 7 rpos 6 tpos 1 rpos 0 tpos 0 rpos 1 mode a2 loop 0 loop 5 mux loop 2 tclk 6 rclk 7 tclk 7 rclk 6 tclk 1 rclk 0 tclk 0 rclk 1 mclk a1 vccio loop 6 loop 7 rv0+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a b c d e f g h j k l m n p a b c d e f g h j k l m n p cs61880 160 fbga (bottom view) los 4 tms gndio rgnd 1 cs los 3 tvcc 5 tvcc 4 tvcc 4 tvcc 5 tvcc 2 tvcc 3 tvcc 3 tvcc 2 rd txoe tck vccio rv1+ wr rdy tclk 5 rclk 4 tclk 4 rclk 5 tclk 2 rclk 3 tclk 3 rclk 2 int los 5 tdi trst intl ale los 2 tneg 5 rneg 4 tneg 4 rneg 5 tneg 2 rneg 3 tneg 3 rneg 2 figure 2. cs61880 160-ball fbga package pin outs
cs61880 ds450pp2 9 3. pin descriptions 3.1 power supplies symbol lqfp fbga type description vccio 17 92 g1 g14 power supply, digital interface: power supply for digital interface pins; typically 3.3v. gndio 18 91 g4 g11 ground, digital interface: power supply ground for the digital interface; typically 0 volts rv0+ rv1+ 19 90 h1 h14 power supply, core circuitry: power supply for all sub-cir- cuits except the transmit driver; typically +3.3 volts rgnd0 rgnd1 20 89 h4 h11 ground, core circuitry: ground for sub-circuits except the tx driver; typically 0 volts tv+0 44 n4, p4 power supply, transmit driver 0 power supply for transmit driver 0; typically +3.3 volts tgnd0 47 n6, p6 ground, transmit driver 0 power supply ground for transmit driver 0; typically 0 volts tv+1 53 l4, m4 power supply, transmit driver 1 tgnd1 50 l6, m6 ground, transmit driver 1 tv+2 56 l11 m11 power supply, transmit driver 2 tgnd2 59 l9, m9 ground, transmit driver 2 tv+3 65 n11 p11 power supply, transmit driver 3 tgnd3 62 n9, p9 ground, transmit driver 3 tv+4 116 a11 b11 power supply, transmit driver 4 tgnd4 119 a9, b9 ground, transmit driver 4 tv+5 125 c11 d11 power supply, transmit driver 5 tgnd5 122 c9, d9 ground, transmit driver 5 tv+6 128 c4, d4 power supply, transmit driver 6 tgnd6 131 c6, d6 ground, transmit driver 6 tv+7 137 a4, b4 power supply, transmit driver 7 tgnd7 134 a6, b6 ground, transmit driver 7
cs61880 10 ds450pp2 3.2 control symbol lqfp fbga type description mclk 10 e1 i master clock input this pin is a free running reference clock that should be 2.048 mhz. this timing reference is used as follows: - timing reference for the clock recovery and jitter attenua- tion circuitry. - rclk reference during loss of signal (los) conditions - transmit clock reference during transmit all ones (taos) condition - wait state timing for microprocessor interface - when this pin is held ?high?, the pll clock recovery cir- cuit is disabled. in this mode, the cs61880 receivers function as simple data slicers. - when this pin is held ?low?, the receiver paths are pow- ered down and the output pins rclk, rpos, and rneg are high-z. mode 11 e2 i mode select this pin is used to select whether the cs61880 operates in serial host, parallel host or hardware mode. host mode - the cs61880 is controlled through either a serial or a parallel microprocessor interface (refer to host mode (see section 13 on page 32). hardware mode - the microprocessor interface is disabled and the device control/status are provided through the pins on the device. note: for serial host mode connect this pin to a resistor divider consisting of two 10k ? resistors between vccio and gndio. table 1. operation mode selection pin state operating mode low hardware mode high parallel host mode vccio/2 serial host mode
cs61880 ds450pp2 11 mux/bitsen0 43 k2 i multiplexed interface/bits clock select host mode - this pin configures the microprocessor inter- face for multiplexed or non-multiplexed operation. hardware mode - this pin is used to enable channel 0 as a g.703 bits clock recovery channel (refer to building integrated timing systems (bits) clock mode (see section 8 on page 23). channel 1 through 7 are not affected by this pin during hardware mode. during host mode the g.703 bits clock recovery function is enabled by the bits clock enable register (1eh) (see section 14.31 on page 40). note: the mux pin only controls the bits clock function in hardware mode int 82 k13 o interrupt output this active low output signals the host processor when one of the cs61880?s internal status register bits has changed state. when the status register is read, the interrupt is cleared. the various status changes that would force int active are maskable via internal interrupt enable registers. note: this pin is an open drain output and requires a 10 k ? pull-up resistor. rdy/ack /sdo 83 k14 o ready/data transfer acknowledge/serial data output intel parallel host mode - during a read or write register access, rdy is asserted ?low? to acknowledge that the de- vice has been accessed. an asserted ?high? acknowledges that data has been written or read. upon completion of the bus cycle, this pin high-z. motorola parallel host mode - during a data bus read operation this pin, ?ack ?, is asserted ?high? to indicate that data on the bus is valid. an asserted ?low? on this pin dur- ing a write operation acknowledges that a data transfer to the addressed register has been accepted. upon comple- tion of the bus cycle, this pin high-z. note: wait state generation via rdy/ack is disabled in rz mode (no clock recovery). serial host mode - when the microprocessor interface is configured for serial bus operation, ?sdo? is used as a seri- al data output. this pin is forced into a high impedance state during a serial write access. the clke pin controls whether sdo is valid on the rising or falling edge of sclk. upon completion of the bus cycle, this pin high-z. hardware mode - this pin is not used and should be left open. symbol lqfp fbga type description table 2. mux/bits clock selection pin state parallel host mode hardware mode high multiplexed bits clock on low non multiplexed bits clock off
cs61880 12 ds450pp2 wr /ds /sdi 84 j14 i write enable/data strobe/serial data intel parallel host mode - this pin, ?wr ?, functions as a write enable. motorola parallel host mode - this pin, ?ds ?, functions as a data strobe input. serial host mode - this pin, ?sdi?, functions as the serial data input. hardware mode - this pin is not used and should be con- nected to ground. rd /rw 85 j13 i read enable/read/write intel parallel host mode - this pin, ?rd ?, functions as a read enable. motorola parallel host mode - this pin, ?r/w ?, functions as the read/write input signal. hardware mode - this pin is not used and should be con- nected to ground. ale/as /sclk 86 j12 i address latch enable/address strobe/serial clock intel parallel host mode - this pin, ?ale?, functions as the address latch enable when configured for multiplexed ad- dress/data operation. motorola parallel host mode - this pin, ?as ?, functions as the active ?low? address strobe when configured for multi- plexed address/data operation. serial host mode - this pin, ?sclk?, is the serial clock used for data i/o on sdi and sdo. hardware mode - this pin is not used and should be con- nected to ground. cs /jasel 87 j11 i chip select input/jitter attenuator select host mode - this active low input is used to enable ac- cesses to the microprocessor interface in either serial or parallel mode. hardware mode - this pin controls the position of the jitter attenuator. symbol lqfp fbga type description table 3. jitter attenuation selection pin state jitter attenuation position low transmit path high receive path open disabled
cs61880 ds450pp2 13 intl/mot /coden 88 h12 i intel/motorola/coder mode select input parallel host mode - when this pin is ?low? the micropro- cessor interface is configured for operation with motorola processors. when this pin is ?high? the microprocessor in- terface is configured for operation with intel processors. hardware mode - when the cs61880 is configured for uni- polar operation, this pin, coden , configures the line encoding/decoding function. when coden is low, hdb3 encoders/decoders are enabled. when coden is high, ami encoding/decoding is activated. this is done for all eight channels. txoe 114 e14 i transmitter output enable host mode - operates the same as in hardware mode. in- dividual drivers can be set to a high impedance state via the output disable register (12h) (see section 14.19 on page 38). hardware mode - when txoe pin is asserted low, all the tx drivers are forced into a high impedance state. all other internal circuitry remains active. clke 115 e13 i clock edge select in clock/data recovery mode, setting clke ?high? will cause rpos/rneg to be valid on the falling edge of rclk and sdo to be valid on the rising edge of sclk. when clke is set ?low?, rpos/rneg is valid on the rising edge of rclk, and sdo is valid on the falling edge of sclk. when the part is operated in data recovery mode, the rpos/rneg output polarity is active ?high? when clke is set ?high? and active ?low? when clke is set ?low?. symbol lqfp fbga type description
cs61880 14 ds450pp2 3.3 address inputs/loopbacks symbol lqfp fbga type description a4 12 f4 i address selector input parallel host mode - during non-multiplexed parallel host mode operation, this pin function as the address 4 input for the parallel interface. hardware mode - the a4 pin must be tied low at all times. a3 a2 a1 a0 13 14 15 16 f3 f2 f1 g3 i i i i non-intrusive monitoring/address selector inputs parallel host mode - during non-multiplexed parallel host mode operation, these pins function as address a[3:0] in- puts for the parallel interface. hardware mode - the a[3:0] pins are used for port selec- tion during non-intrusive monitoring. in non-intrusive monitoring mode, receiver 0?s input is internally connected to the transmit or receive ports on one of the other 7 chan- nels. the recovered clock and data from the selected port are output on rpos0/rneg0 and rclk0. additionally, the data from the selected port can be output on ttip0/tring0 by activating the remote loopback function for channel 0 (refer to performance monitor register (0bh) (see section 14.12 on page 36). loop0/d0 loop1/d1 loop2/d2 loop3/d3 loop4/d4 loop5/d5 loop6/d6 loop7/d7 21 22 23 24 25 26 27 28 g2 h3 h2 j4 j3 j2 j1 k1 i/o i/o i/o i/o i/o i/o i/o i/o loopback mode selector/parallel data input/output parallel host mode - in non-multiplexed microprocessor in- terface mode, these pins function as the bi-directional 8-bit data port. when operating in multiplexed microprocessor in- terface mode, these pins function as the address and data inputs/outputs. hardware mode - no loopback - the cs61880 is in a normal operating state when loop is left open (unconnected) or tied to vccio/2. - local loopback - when loop is tied high, data transmit- ted on ttip and tring is looped back into the analog input of the corresponding channel?s receiver and output on rpos and rneg. input data present on rtip and rring is ignored. - remote loopback - when loop is tied low the recov- ered clock and data received on rtip and rring is looped back for transmission on ttip and tring. data on tpos and tneg is ignored.
cs61880 ds450pp2 15 3.4 cable select 3.5 status symbol lqfp fbga type description cblsel 93 g13 i cable impedance select host mode - the input voltage to this pin does not effect normal operation. hardware mode - this pin is used to select the transmitted pulse shape and set the line impedance for all eight receiv- ers and transmitters. this pin also selects whether or not all eight receivers use an internal or external line matching network (refer to the table 4 below for proper settings). note: refer to figure 16 on page 50 and figure 17 on page 51 for appropriate external line matching com- ponents. all transmitters use internal matching net- works. table 4. cable impedance selection cblsel transmitters receivers no connect 120 ? internal 120 ? internal or external high 75 ? internal 75 ? internal low 75 ? internal 75 ? external symbol lqfp fbga type description los0 los1 los2 los3 los4 los5 los6 los7 42 35 75 68 113 106 3 140 k4 k3 k12 k11 e11 e12 e3 e4 o o o o o o o o loss of signal output the los output pins can be configured to indicate a loss of signal (los) state that is compliant to either itu g.775 or etsi 300 233. these pins are asserted ?high? to indicate los. the los output returns low when an input signal is present for the time period dictated by the associated speci- fication (refer to loss-of-signal (los) (see section 10.5 on page 27)).
cs61880 16 ds450pp2 3.6 digital rx/tx data i/o symbol lqfp fbga type description tclk0 36 n1 i transmit clock input port 0 - when tclk is active, the tpos and tneg pins function as nrz inputs that are sampled on the falling edge of tclk. - if mclk is active, taos will be generated when tclk is held high for 16 mclk cycles. note: mclk is used as the timing reference during taos and must have the appropriate stability. - if tclk is held high in the absence of mclk, the tpos and tneg inputs function as rz inputs. in this mode, the transmit pulse width is set by the pulse-width of the signal input on tpos and tneg. to enter this mode, tclk must be held high for at least 12 s. - if tclk is held low, the output drivers enter a low-power, high impedance state. tpos0/tdata0 tneg0/ubs 37 38 n2 n3 i i transmit positive pulse/transmit data input port 0 transmit negative pulse/unipolar-bipolar select port 0 the function of the tpos/tdata and tneg/ubs inputs are determined by whether unipolar, bipolar or rz input mode has been selected. bipolar mode - in this mode, nrz data on tpos and tneg are sampled on the falling edge of tclk and trans- mitted onto the line at ttip and tring respectively. a ?high? input on tpos results in transmission of a positive pulse; a ?high? input on tneg results in a transmission of a negative pulse. the translation of tpos/tneg inputs to ttip/tring outputs is as follows: unipolar mode - unipolar mode is activated by holding tneg/ubs ?high? for more than 16 tclk cycles, when mclk is present. the falling edge of tclk samples a uni- polar data steam on tpos/tdata. rz mode - to activate rz mode tie tclk ?high? in the absence of mclk. in this mode, the duty cycle of the tpos and tneg inputs determine the pulse width of the output signal on ttip and tring. table 5. bipolar mode translations tpos tneg output 00 space 1 0 positive mark 0 1 negative mark 11 space
cs61880 ds450pp2 17 rclk0 39 p1 o receive clock output port 0 - when mclk is active, this pin outputs the recovered clock from the signal input on rtip and rring. in the event of los, the rclk output transitions from the recovered clock to mclk. - if mclk is held ?high?, the clock recovery circuitry is dis- abled and the rclk output is driven by the xor of rneg and rpos. - if mclk is held ?low?, this output is in a high-impedance state. rpos0/rdata0 rneg0/bpv0 40 41 p2 p3 o o receive positive pulse/ receive data output port 0 receive negative pulse/bipolar violation output port 0 the function of the rpos/rdata and rneg/bpv outputs are determined by whether unipolar, bipolar, or rz input mode has been selected. during los, the rpos/rneg outputs will remain active. note: the rpos/rneg outputs can be high-z by holding mclk low. bipolar output mode - when configured for bipolar opera- tion, nrz data is recovered from rtip/rring and output on rpos/rneg. a high signal on rpos or rneg corre- spond to the receipt of a positive or negative pulse on rtip/rring respectively. the rpos/rneg outputs are valid on the falling or rising edge of rclk as configured by clke. unipolar output mode - when unipolar mode is activated, the recovered data is output on rdata. the decoder sig- nals bipolar violations are output on the rneg/bpv pin. rz output mode - in this mode, the rpos/rneg pins output rz data recovered by slicing the signal present on rtip/rring. a positive pulse on rtip with respect to rring generates a logic 1 on rpos; a positive pulse on rring with respect to rtip generates a logic 1 on rneg. the polarity of the output on rpos/rneg is selectable us- ing the clke pin. in this mode, external circuitry is used to recover clock from the received signal. tclk1 29 l1 i transmit clock input port 1 tpos1/tdata1 30 l2 i transmit positive pulse/transmit data input port 1 tneg1/ubs1 31 l3 i transmit negative pulse/unipolar-bipolar select port 1 rclk1 32 m1 o receive clock output port 1 rpos1/rdata1 33 m2 o receive positive pulse/ receive data output port 1 rneg1/bpv1 34 m3 o receive negative pulse/bipolar violation output port 1 tclk2 81 l14 i transmit clock input port 2 tpos2/tdata2 80 l13 i transmit positive pulse/transmit data input port 2 tneg2/ubs2 79 l12 i transmit negative pulse/unipolar-bipolar select port 2 symbol lqfp fbga type description
cs61880 18 ds450pp2 rclk2 78 m14 o receive clock output port 2 rpos2/rdata2 77 m13 o receive positive pulse/ receive data output port 2 rneg2/bpv2 76 m12 o receive negative pulse/bipolar violation output port 2 tclk3 74 n14 i transmit clock input port 3 tpos3/tdata3 73 n13 i transmit positive pulse/transmit data input port 3 tneg3/ubs3 72 n12 i transmit negative pulse/unipolar-bipolar select port 3 rclk3 71 p14 o receive clock output port 3 rpos3/rdata3 70 p13 o receive positive pulse/ receive data output port 3 rneg3/bpv3 69 p12 o receive negative pulse/bipolar violation output port 3 tclk4 107 b14 i transmit clock input port 4 tpos4/tdata4 108 b13 i transmit positive pulse/transmit data input port 4 tneg4/ubs4 109 b12 i transmit negative pulse/unipolar-bipolar select port 4 rclk4 110 a14 o receive clock output port 4 rpos4/rdata4 111 a13 o receive positive pulse/ receive data output port 4 rneg4/bpv4 112 a12 o receive negative pulse/bipolar violation output port 4 tclk5 100 d14 i transmit clock input port 5 tpos5/tdata5 101 d13 i transmit positive pulse/transmit data input port 5 tneg5/ubs5 102 d12 i transmit negative pulse/unipolar-bipolar select port 5 rclk5 103 c14 o receive clock output port 5 rpos5/rdata5 104 c13 o receive positive pulse/ receive data output port 5 rneg5/bpv5 105 c12 o receive negative pulse/bipolar violation output port 5 tclk6 9 d1 i transmit clock input port 6 tpos6/tdata6 8 d2 i transmit positive pulse/transmit data input port 6 tneg6/ubs6 7 d3 i transmit negative pulse/unipolar-bipolar select port 6 rclk6 6 c1 o receive clock output port 6 rpos6/rdata6 5 c2 o receive positive pulse/ receive data output port 6 rneg6/bpv6 4 c3 o receive negative pulse/bipolar violation output port 6 tclk7 2 b1 i transmit clock input port 7 tpos7/tdata7 1 b2 i transmit positive pulse/transmit data input port 7 tneg7/ubs7 144 b3 i transmit negative pulse/unipolar-bipolar select port 7 symbol lqfp fbga type description
cs61880 ds450pp2 19 3.7 analog rx/tx data i/o rclk7 143 a1 o receive clock output port 7 rpos7/rdata7 142 a2 o receive positive pulse/ receive data output port 7 rneg7/bpv7 141 a3 o receive negative pulse/bipolar violation output port 7 symbol lqfp fbga type description symbol lqfp fbga type description ttip0 tring0 45 46 n5 p5 o o transmit tip output port 0 transmit ring output port 0 these pins are the differential outputs of the transmit driver. the driver internally matches impedances for e1 75 ? or e1 120 ? lines requiring only a 1:1.15 transformer. the cblsel pin is used to select the appropriate line matching impedance only in ?hardware? mode. in host mode, the ap- propriate line matching impedance is selected by the line length data register (11h) (see section 14.18 on page 38). note: ttip and tring are forced to a high impedance state when the tclk or the txoe pin is forced ?low?. rtip0 rring0 48 49 p7 n7 i i receive tip input port 0 receive ring input port 0 these pins are the differential line inputs to the receiver. the receiver uses either internal line impedance or exter- nal line impedance modes to match the line impedances for e1 75 ? or e1 120 ? modes. internal line impedance mode - the receiver uses the same external resistors to match the line impedance (refer to figure 16 on page 50 ). external line impedance mode - the receiver uses differ- ent external resistors to match the line impedance (refer to figure 17 on page 51 ). - in host mode, the appropriate line impedance is selected by the line length data register (11h) (see section 14.18 on page 38). - in hardware mode, the cblsel pin selects the appropri- ate line impedance. (refer to table 4 on page 15 for proper line impedance settings). note: data and clock recovered from the signal input on these pins are output via rclk, rpos, and rneg. ttip1 52 l5 o transmit tip output port 1 tring1 51 m5 o transmit ring output port 1 rtip1 55 m7 i receive tip input port 1 rring1 54 l7 i receive ring input port 1 ttip2 57 l10 o transmit tip output port 2
cs61880 20 ds450pp2 tring2 58 m10 o transmit ring output port 2 rtip2 60 m8 i receive tip input port 2 rring2 61 l8 i receive ring input port 2 ttip3 64 n10 o transmit tip output port 3 tring3 63 p10 o transmit ring output port 3 rtip3 67 p8 i receive tip input port 3 rring3 66 n8 i receive ring input port 3 ttip4 117 b10 o transmit tip output port 4 tring4 118 a10 o transmit ring output port 4 rtip4 120 a8 i receive tip input port 4 rring4 121 b8 i receive ring input port 4 ttip5 124 d10 o transmit tip output port 5 tring5 123 c10 o transmit ring output port 5 rtip5 127 c8 i receive tip input port 5 rring5 126 d8 i receive ring input port 5 ttip6 129 d5 o transmit tip output port 6 tring6 130 c5 o transmit ring output port 6 rtip6 132 c7 i receive tip input port 6 rring6 133 d7 i receive ring input port 6 ttip7 136 b5 o transmit tip output port 7 tring7 135 a5 o transmit ring output port 7 rtip7 139 a7 i receive tip input port 7 rring7 138 b7 i receive ring input port 7 symbol lqfp fbga type description
cs61880 ds450pp2 21 3.8 jtag test interface 3.9 miscellaneous symbol lqfp fbga type description trst 95 g12 i jtag reset this active low input resets the jtag controller. this input is pulled up internally and may be left as a nc when not used. tms 96 f11 i jtag test mode select input this input enables the jtag serial port when active high. this input is sampled on the rising edge of tck. this input is pulled up internally and may be left as a nc when not used. tck 97 f14 i jtag test clock data on tdi is valid on the rising edge of tck. data on tdo is valid on the falling edge of tck. when tck is stopped high or low, the contents of all jtag registers re- main unchanged. tie pin low through a 10 k ? resistor when not used. tdo 98 f13 o jtag test data output jtag test data is shifted out of the device on this pin. data is output on the falling edge of tck. leave as nc when not used. tdi 99 f12 i jtag test data input jtag test data is shifted into the device using this pin. the pin is sampled on the rising edge of tck. tdi is pulled up internally and may be left as a nc when not used. symbol lqfp fbga type description ref 94 h13 i reference input this pin must be tied to ground through 13.3 k ? 1% resis- tor. this pin is used to set the internal current level.
cs61880 22 ds450pp2 4. operation the cs61880 is a full featured line interface unit for up to eight e1 75 ? or e1 120 ? lines. the de- vice provides an interface to twisted pair or co-ax- ial media. a matched impedance technique is employed that reduces power and eliminates the need for matching resistors. as a result, the device can interface directly to the line through a trans- former without the need for matching resistors on the transmit side. the receive side uses the same re- sistor values for all e1 settings. 5. power-up on power-up, the device is held in a static state un- til the power supply achieves approximately 70% of the power supply voltage. once the power sup- ply threshold is passed, the analog circuitry is cali- brated, the control registers are reset to their default settings, and the various internal state machines are reset. the reset/calibration process completes in about 30 ms. 6. master clock the cs61880 requires a 2.048 mhz reference clock with a minimum accuracy of 100 ppm. this clock may be supplied from internal system timing or a cmos crystal oscillator and input to the mclk pin. the receiver uses mclk as a reference for clock recovery, jitter attenuation, and the generation of rclk during los. the transmitter uses mclk as the transmit timing reference during a blue alarm transmit all ones condition. in addition, mclk provides the reference timing for wait state genera- tion. in systems with a jittered transmit clock, mclk should not be tied to the transmit clock, a separate crystal oscillator should drive the reference clock input. any jitter present on the reference clock will not be filtered by the jitter attenuator and can cause the cs61880 to operate incorrectly. 7. g.772 monitoring the receive path of channel zero of the cs61880 can be used to monitor the receive or transmit paths of any of the other channels. the signal to be mon- itored is multiplexed to channel zero through the g.772 multiplexer. the multiplexer and channel zero then form a g.772 compliant digital protected monitoring point (pmp). when the pmp is connect- ed to the channel, the attenuation in the signal path is negligible across the signal band. the signal can be observed using rpos, rneg, and rclk of chan- nel zero or by putting channel zero in remote loop- back, the signal can be observed on ttip and tring of channel zero. the g.772 monitoring function is available during both host mode and hardware mode operation. in host modes, individual channels are selected for monitoring via the performance monitor regis- ter (0bh) (see section 14.12 on page 36)). in hard- ware mode, individual channels are selected through the a3:a0 pins (refer to table 6 below for address settings). note: in hardware mode the a4 pin must be tied low at all times. table 6. g.772 address selection address [a3:a0] channel selection 0000 monitoring disabled 0001 receiver channel # 1 0010 receiver channel # 2 0011 receiver channel # 3 0100 receiver channel # 4 0101 receiver channel # 5 0110 receiver channel # 6 0111 receiver channel # 7 1000 monitoring disabled 1001 transmitter channel # 1 1010 transmitter channel # 2 1011 transmitter channel # 3 1100 transmitter channel # 4 1101 transmitter channel # 5 1110 transmitter channel # 6 1111 transmitter channel # 7
cs61880 ds450pp2 23 8. building integrated timing systems (bits) clock mode this mode is used to enable one or more channels as a stand-alone timing recovery unit used for g.703 clock recovery. in hardware mode, bits clock mode is selected by pulling the mux pin ?high?. this enables only channel zero as a stand-alone timing recovery unit, no other channel can be used as a timing recovery unit. in host mode, each channel can be setup as an inde- pendent g.703 timing recovery unit, through the bits clock enable register (1eh) (see section 14.31 on page 40), setting the desired bit to ?1? en- ables bits clock mode for that channel. the fol- lowing diagrams show how the bits clock function operates. t1 1:2 rring r1 r2 receive line 0.1 f cs61880 one receiver rtip rclk rpos rneg figure 3. g.703 bits clock mode in nrz mode t1 1:2 rring r1 r2 receive line 0.1 f cs61880 one receiver rtip rclk rpos rneg figure 4. g.703 bits clock mode in rz mode t1 1:2 rring r1 r2 receive line 0.1 f cs61880 one channel rtip rclk rpos rneg tclk tpos tneg remote loopback t1 1:1.15 tranmit line tring ttip figure 5. g.703 bits clock mode in remote loopback
cs61880 24 ds450pp2 9. transmitter the cs61880 contains eight identical transmitters that each use a low power matched impedance driv- er to eliminate the need for external load matching resistors, while providing superior return loss. as a result, the ttip/tring outputs can be connected directly to the transformer allowing one hardware circuit for e1 120 ? , and e1 75 ? applications. digital transmit data and clock are input into the cs61880 through the tpos/tdata, tneg and tclk input pins. these pins accept data in one of three formats: unipolar, bipolar, or rz. in either unipolar or bipolar mode, the cs61880 internally generates a pulse shape compliant to the g.703 mask for e1 (refer to figure 6 ). the pulse shaping applied to the transmit data can be selected in hard- ware mode or in host mode. in hardware mode, the line impedance (75 ? or 120 ? ) and which prestored pulse shape to transmit (75 ? or 120 ? ) is selected via the cblsel pin for all eight transmitters. in host mode, each channel is configured indepen- dently by writing to the line length channel id register (10h) (see section 14.17 on page 38), then writing the desired line length settings to the len[3:0] bits in the line length data register (11h) (see section 14.18 on page 38). the len bits select the pulse shape and line impedance of the addressed channel. in host mode, the cblsel pin is not used. note: if one channel is configured for e1 75 ? mode, another channel can be configured for e1 120 ? mode at the same time. this operation is only allowed in host mode. the cs61880 also allows the user to customize the transmit pulse shapes to compensate for non-stan- dard cables, transformers, or protection circuitry. for further information on the awg refer to ar- bitrary waveform generator (see section 15 on page 42). for more information on the host mode registers re- fer to register descriptions (see section 14 on page 35) . 9.1 bipolar mode bipolar mode provides transparent operation for applications in which the line coding function is performed by an external framing device. in this mode, the falling edge of tclk samples nrz data on tpos/tneg for transmission on ttip/tring. 9.2 unipolar mode in unipolar mode, the cs61880 is configured such that transmit data is encoded using hdb3, or ami line codes. this mode is activated by holding 269 ns 244 ns 194 ns 219 ns 488 ns nominal pulse 0 10 50 80 90 100 110 120 -10 -20 percent of nominal peak voltage figure 6. pulse mask at e1 interface
cs61880 ds450pp2 25 tneg/ubs ?high? for more than 16 tclk cy- cles. transmit data is input to the part via the tpos/tdata pin on the falling edge of tclk. when operating the part in hardware mode, the coden pin is used to select between hdb3 or ami encoding. during host mode operation, the line coding is selected via the line length chan- nel id register (10h) (see section 14.17 on page 38). note: the encoders/decoders are selected for all eight channels in both hardware and host mode. 9.3 rz mode in rz mode, the internal pulse shape circuitry is bypassed and rz data driven into tpos/tneg is transmitted on ttip/tring. in this mode, the pulse width of the transmitter output is determined by the width of the rz signal input to tpos/tneg pins. this mode is entered when mclk is inactive and tclk is held ?high? for at least 12 sec. 9.4 transmitter powerdown / high-z the transmitters can be forced into a high imped- ance, low power state by holding tclk of the ap- propriate channel low for at least 12 s or 140 mclk cycles. in hardware and host mode, the txoe pin forces all eight transmitters into a high impedance state within 1 s. in host mode, each transmitter is individually con- trollable using the output disable register (12h) (see section 14.19 on page 38). the txoe pin can be used in host mode, but does not effect the con- tents of the output enable register. this feature is useful in applications that require redundancy. 9.5 transmit all ones (taos) when taos is activated, continuous ones are transmitted on ttip/tring using mclk as the transmit timing reference. in this mode, the tpos and tneg inputs are ignored. in hardware mode, taos is activated by pulling tclk ?high? for more than 16 mclk cycles. in host mode, taos is generated for a particular channel by asserting the associated bit in the taos enable register (03h) (see section 14.4 on page 35). since mclk is the reference clock, it should be of adequate stability. 9.6 automatic taos while a given channel is in the los condition, if the corresponding bit in the automatic taos register (0eh) (see section 14.15 on page 37) is set, the device will drive that channel?s ttip and tring with the all ones pattern. this function is only available in host mode. refer to loss-of-sig- nal (los) (see section 10.5 on page 27). 9.7 driver failure monitor in host mode, the driver failure monitor (dfm) function monitors the output of each channel and sets a bit in the dfm status register (05h) (see section 14.6 on page 35) if a secondary short cir- cuit is detected between ttip and tring. this generates an interrupt if the respective bit in the dfm interrupt enable register (07h) (see sec- tion 14.8 on page 36) is also set. any change in the dfm status register (05h) (see section 14.6 on page 35) will result in the corresponding bit in the dfm interrupt status register (09h) (see sec- tion 14.10 on page 36) being set. the interrupt is cleared by reading the dfm interrupt status register (09h) (see section 14.10 on page 36). 9.8 driver short circuit protection the cs61880 provides driver short circuit protec- tion when current on the secondary exceeds 50 ma rms.
cs61880 26 ds450pp2 10. receiver the cs61880 contains eight identical receivers that utilize an internal matched impedance technique that provides for the use of a common set of exter- nal components for 120 ? (e1), and 75 ? (1) op- eration (refer to figure 16 on page 50 ). this feature enables the use of a one stuffing option for all e1 line impedances. the receivers can also be configured to use different external resistors to match the line impedance for e1 75 ? or e1 120 ? modes (refer to figure 17 on page 51 ). in hardware mode, the cblsel pin is used to se- lect the proper line impedance (75 ? or 120 ? ) and either internal or external line impedance matching mode. in host mode, each receiver?s line impedance is se- lected individually via the line length channel id register (10h) (see section 14.17 on page 38) and bits[3:0] and the len[3:0] bits of the line length data register (11h) (see section 14.18 on page 38). the int_extb bit of the line length data register (11h) (see section 14.18 on page 38) is used to select between internal or exter- nal line impedance matching modes for all eight channels. the cblsel pin is not used in host mode. the cs61880 receiver provides all of the circuitry to recover both data and clock from the data signal input on rtip and rring. the matched imped- ance receiver is capable of recovering signals with 12 db of attenuation (referenced to 2.37 v or 3.0v nominal) while providing superior return loss. in addition, the timing recovery circuit along with the jitter attenuator provide jitter tolerance that far ex- ceeds jitter specifications (refer to figure 19 on page 57 ). the recovered data and clock are output from the cs61880 on the rpos/rdata, rneg and rclk pins. these pins output the data in one of three formats: bipolar, unipolar, or rz. the clke pin is used to configure rpos/rdata and rneg, so that data is valid on either the rising or falling edge of rclk. refer to the clke pin de- scription on page 13 for clke settings. 10.1 bipolar output mode bipolar mode provides a transparent clock/data re- covery for applications in which the line decoding is performed by an external framing device. the re- covered clock and data are output on rclk, rneg and rpos. 10.2 unipolar output mode in unipolar mode, the cs61880 decodes the recov- ered data with either hdb3 or ami line decoding. the decoded data is output on the rpos/rdata pin. when bipolar violations are detected by the de- coder, the rneg/bpv pin is asserted ?high?. this pin is driven ?high? for one rclk period for every bipolar violation that is not part of the zero substi- tution rules. unipolar mode is entered by holding the tneg pin ?high? for more than 16 tclk cy- cles. in hardware mode, the hdb3/ami encoding/de- coding is activated via the coden pin. in host mode, bit 4 of the line length channel id register (10h) (see section 14.17 on page 38) is used to select the encoding/decoding for all chan- nels. 10.3 rz output mode in this mode the rtip and rring inputs are sliced to data values that are output on rpos and rneg pins. this mode is used in applications that have clock recovery circuitry external to the device. to support external clock recovery, the rpos and rneg outputs are xored and output as rclk. this mode is entered when mclk is tied high. the polarity of the rpos/rneg data are controlled by the clke pin. refer to the clke pin description on page 13 for clke settings.
cs61880 ds450pp2 27 10.4 receiver powerdown/high-z all eight receivers are powered down when mclk is held low. in addition, this will force the rclk, rpos/rdata and rneg outputs into a high im- pedance state. 10.5 loss-of-signal (los) the cs61880 makes use of both analog and digital los detection circuitry that is compliant to the lat- est specifications. the los condition can be set to either itu g.775 or etsi 300 233. this change is done through the los/ais mode enable regis- ter (0dh) (see section 14.14 on page 37). the los detector increments a counter each time a zero is received, and resets the counter each time a one ?mark? is received. depending on los detec- tion mode, the los signal is set when a certain number of consecutive zeros are received. in clock/data recovery mode, this forces the recov- ered clock to be replaced by mclk at the rclk output. in addition the rpos/rdata and rneg outputs remain active for the length of the los pe- riod, except when local and analog loopbacks are enabled. upon exiting los, the recovered clock re- places mclk on the rclk output. in data recov- ery mode, rclk is not replaced by mclk when los is active. the los detection modes are sum- marized below. note: g.775 and etsi 300 233 are both available in host mode, but in hardware mode only etsi 300 233 is available. itu g.775 (e1 mode only) - los is declared when the received signal level is less than 200 mv for 32 consecutive pulse periods (typical). the de- vice exits los when the received signal achieves 12.5% ones density with no more than 15 consecu- tive zeros in a 32-bit sliding window and the signal level exceeds 250 mv. etsi 300 233 (e1 host mode only) - the los indicator becomes active when the receive signal level drops below 200 mv for more than 2048 pulse periods (1 msec). the channel exits the los state when the input signal exceeds 250 mv and has transitions for more than 32 pulse periods (16 sec). this los detection method can only be selected while in host mode. during host mode operation, los is reported in the los status monitor register. both the los pins and the register bits reflect los status in host mode operation. the los pins and status bits are set high (indicating loss of signal) during reset, power-up, or channel powered-down. 10.6 alarm indication signal (ais) the cs61880 detects all ones alarm condition per the relevant itu, and etsi specifications. in gen- eral, ais is indicated when the one?s density of the receive signal exceeds that dictated by the relevant specification. this feature is only available in host mode (refer to los/ais mode enable register (0dh) (see section 14.14 on page 37)). itu g.775 ais (e1 mode) - the ais condition is declared when less than 3 zeros are received within two consecutive 512-bit windows. the ais condi- tion is cleared when 3 or more zeros are received in two consecutive 512-bit windows. etsi 300 233 (e1 mode) - the ais condition is declared when less than 3 zeros are received in a 512-bit window. the ais condition is cleared when a 512-bit window is received containing 3 or more zeros.
cs61880 28 ds450pp2 11. jitter attenuator the cs61880 internal jitter attenuators can be switched into either the receive or transmit paths. alternatively, it can be removed from both paths to reduce the propagation delay. during hardware mode operation, the location of the jitter attenuator for all eight channels are con- trolled by the jasel pin (refer to table 7 for pin configurations). the jitter attenuator?s fifo length and corner frequency, can not be changed in hard- ware mode. the fifo length and corner frequency are set to 32 bits and 1.25 hz. during host mode operation, the location of the jit- ter attenuator for all eight channels are set by bits 0 and 1 in the line length channel id register (10h) (see section 14.17 on page 38). this register (0fh) also configures the jitter attenuator?s fifo length (bit 3) and corner frequency (bit 2). the attenuator consists of a 64-bit fifo, a narrow- band monolithic pll, and control logic. the jitter attenuator requires no external crystal. signal jitter is absorbed in the fifo which is designed to nei- ther overflow nor underflow. if overflow or underflow is imminent, the jitter transfer function is altered to ensure that no bit-er- rors occur. a configuration option is provided to reduce the jitter attenuator fifo length from 64 bits to 32 bits in order to reduce propagation delay. the jitter attenuator -3 db knee frequency depends on the settings of the jitter attenuator fifo length and the jitter attenuator corner frequency, bits 2 and 3, in the line length channel id register (10h) (see section 14.17 on page 38)). setting the lowest corner frequency guarantees jitter attenua- tion compliance to european specifications tbr 12/13 and ets 300 011. the jitter attenuator is also compliant with itu-t g.735, g.742, and g.783 (refer to figure 18 on page 56 and figure 19 on page 57 ). table 7. jitter attenuator configurations pin state jitter attenuator positon low transmit path high receive path open disabled
cs61880 ds450pp2 29 12. operational summary a brief summary of the cs61880 operations in hardware and host mode is provided in table 8 . 12.1 loopbacks the cs61880 provides three loopback modes for each port. analog loopback connects the transmit signal on ttip and tring to rtip and rring. digital loopback connects the output of the en- coder to the input of the decoder (through the jitter attenuator if enabled). remote loopback connects the output of the clock and data recovery block to the input of the pulse shaper block. (refer to de- tailed descriptions below.) in hardware mode, the loop[7:0] pins are used to activate analog or re- mote loopback for each channel. in host mode, the analog, digital and remote loopback registers are used to enable these functions (refer to the analog loopback register (01h) (see section 14.2 on page 35), remote loopback register (02h) (see section 14.3 on page 35), and digital loopback reset register (0ch) (see section 14.13 on page 36). 12.2 analog loopback in analog loopback, the output of the ttip/tring driver is internally connected to the input of the rtip/rring receiver so that the data on tpos/tneg and tclk appears on the rpos/rneg and rclk outputs. in this mode the rtip and rring inputs are ignored. refer to figure 7 on page 30 . in hardware mode, analog loopback is selected by driving loop[7:0] high. in host mode, analog loopback is selected for a given channel using the appropriate bit in the ana- log loopback register (01h) (see section 14.2 on page 35). note: the simultaneous selection of analog and remote loopback modes is not valid. a taos request overrides the data on tpos and tneg during analog loopback. refer to figure 8 on page 30 . table 8. operational summary mclk tclk loop receive mode transmit mode loopback active active open rclk/data recovery unipolar/bipolar disabled active active l rclk/data recovery unipolar/bipolar remote loopback active active h rclk/data recovery unipolar/bipolar analog loopback active l x rclk/data recovery power down disabled active h open rclk/data recovery taos disabled active h l rclk/data recovery unipolar/bipolar remote loopback active h h rclk/data recovery taos analog loopback l active x power down unipolar/bipolar disabled l h x power down rz data disabled l l x power down power down disabled h active open data recovery unipolar/bipolar disabled h active l data recovery rz data remote loopback h active h data recovery unipolar/bipolar analog loopback h l open data recovery power down disabled h l l data recovery rz data remote loopback h l h data recovery power down disabled h h open data recovery rz data disabled h h l data recovery rz data remote loopback h h h data recovery rz data analog loopback
cs61880 30 ds450pp2 12.3 digital loopback digital loopback causes the tclk, tpos, and tneg (or tdata) inputs to be looped back through the jitter attenuator (if enabled) to the rclk, rpos, and rneg (or rdata) outputs. the receive line interface is ignored, but data at tpos and tneg (or tdata) continues to be transmitted to the line interface at ttip and tring (refer to figure 9 on page 31 ). digital loopback is only available during host mode. it is selected using the appropriate bit in the digital loopback reset register (0ch) (see sec- tion 14.13 on page 36). note: taos can also be used during the digital loop- back operation for the selected channel (refer to figure 10 on page 31 ). 12.4 remote loopback in remote loopback, the rpos/rneg and rclk outputs are internally input to the transmit circuits for output on ttip/tring. in this mode the tclk, tpos and tneg inputs are ignored. (refer to figure 11 on page 31 ) . in hardware mode, re- mote loopback is selected by driving the loop pin for a certain channel low. in host mode, remote loopback is selected for a given channel by writing a one to the appropriate bit in the remote loop- back register (02h) (see section 14.3 on page 35). note: in hardware mode, remote loopback over- rides taos for the selected channel. in host mode, taos overrides remote loopback. encoder decoder ttip tring rtip rring tneg tclk rneg rclk tpos rpos clock recovery & data recovery transmit control & pulse shaper jitter attenuator jitter attenuator figure 7. analog loopback block diagram encoder decoder tneg tclk rneg rclk tpos rpos taos mclk (all one's) ttip tring rtip rring clock recovery & data recovery transmit control & pulse shaper jitter attenuator jitter attenuator figure 8. analog loopback with taos block diagram
cs61880 ds450pp2 31 encoder decoder tneg tclk rneg rclk tpos rpos ttip tring rtip rring clock recovery & data recovery transmit control & pulse shaper jitter attenuator jitter attenuator figure 9. digital loopback block diagram taos mclk encoder decoder tneg tclk rneg rclk tpos rpos ttip tring rtip rring clock recovery & data recovery transmit control & pulse shaper jitter attenuator jitter attenuator (all one's) figure 10. digital loopback with taos encoder decoder tneg tclk rneg rclk tpos rpos ttip tring rtip rring clock recovery & data recovery transmit control & pulse shaper jitter attenuator jitter attenuator figure 11. remote loopback block diagram
cs61880 32 ds450pp2 13. host mode host mode allows the cs61880 to be configured and monitored using an internal register set. (refer to table 1, ?operation mode selection,? on page 10 ). the term, ?host mode? applies to both parallel host and serial host modes. all of the internal registers are available in both se- rial and parallel host mode; the only difference is in the functions of the interface pins, which are de- scribed in table 9 on page 32 . serial port operation is compatible with the serial ports of most microcontrollers. parallel port opera- tion can be configured to be compatible with 8-bit microcontrollers from motorola or intel, with both multiplexed or non-multiplexed address/data bus- ses. (refer to table 10 on page 34 for host mode registers). 13.1 software reset a software reset can be forced by writing the soft- ware reset register (0ah) (see section 14.11 on page 36). a software reset initializes all registers to their default settings and initializes all internal state machines. 13.2 serial port operation serial port host mode operation is selected when the mode pin is left open or set to vcc/2. in this mode, the cs61880 register set is accessed by set- ting the chip select (cs ) pin low and communicat- ing over the sdi, sdo, and sclk pins. timing over the serial port is independent of the transmit and receive system timing. figure 12 illustrates the format of serial port data transfers. a read or write is initiated by writing an ad- dress/command byte (acb) to sdi. only the adr0-adr4 bits are valid; bits adr5-adr6 are do not cares. during a read cycle, the register data addressed by the acb is output on sdo on the next eight sclk clock cycles. during a write cycle, the data byte immediately follows the acb. data is written to and read from the serial port in lsb first format. when writing to the port, sdi data is sampled by the device on the rising edge of sclk. the valid clock edge of the data on sdo is controlled by the clke pin. when clke is low, data on sdo is valid on the falling edge of sclk. when clke is high, data on sdo is valid on the raising edge of sclk. the sdo pin is high-z when not transmitting. if the host processor has a table 9. host control signal descriptions host control signal descriptions pin name pin # hardware serial parallel mode 11 low vdd/2 high mux 43 bitsen0 - mux coden /mot /intl 88 coden -mot /intl addr [4] 12 gnd - addr[4] addr[3:0] 13-16 addr[3:0] - addr [3:0] loop[7:0], data[7:0] 28-21 loop[7:0] - data[7:0] int 82 pulled up int int sdo/ack /rdy 83 nc sdo ack /rdy sdi/ds /wr 84 gnd sdi ds /wr r/w /rd 85 gnd - r/w /rd sclk/as /ale 86 gnd sclk as /ale jasel/cs 87 jasel cs cs
cs61880 ds450pp2 33 bidirectional i/o port, sdi and sdo may be tied to- gether. as illustrated in figure 12 , the acb consists of a r/w bit, address field, and two reserved bits. the r/w bit specifies if the current register access is a read (r/w = 1) or a write (r/w = 0) operation. the address field specifies the register address from 0x00 to 0x1f. 13.3 parallel port operation parallel port host mode operation is selected when the mode pin is high. in this mode, the cs61880 register set is accessed using an 8-bit, multiplexed bidirectional address/data bus d[7:0]. timing over the parallel port is independent of the transmit and receive system timing. the device is compatible with both intel and mo- torola bus formats. the intel bus format is selected when the intl/mot pin is high and the motorola bus format is selected when the intl/mot pin is low. in either mode, the interface can have the ad- dress and data multiplexed over the same 8-bit bus or on separate busses. this operation is controlled with the mux pin; mux = 1 means that the paral- lel port has its address and data multiplexed over the same bus; mux = 0 defines a non-multiplexed bus. the timing for the different modes are shown in figure 28 , figure 27 , figure 25 , figure 26 , figure 30 , figure 29 , figure 32 and figure 31 . multiplexed intel and motorola modes are shown in figure 28 , figure 27 , figure 25 and figure 26 . a read or write is initiated by writing an address byte to d[7:0]. the device latches the address on the falling edge of ale(as ). during a read cycle, the register data is output during the later portion of the rd or ds pulses. the read cycle is terminated and the bus returns to a high impedance state as rd transitions high in intel timing or ds transitions high in motorola timing. during a write cycle, val- id write data must be present and held stable during the wr or ds pulses. non-multiplexed intel and motorola modes are shown in figure 30 , figure 29 , figure 31 and figure 32 . the cs pin initiates the cycle, followed by the ds , rd or wr pin. data is latched into or out of the part using the rising edge of the ds , wr or rd pin. raising cs ends the cycle. in intel mode, the rdy output pin is normally in a high impedance state; it pulses low once to ac- knowledge that the chip has been selected, and high again to acknowledge that data has been written or read. in motorola mode, the ack pin performs a similar function; it drives high to indicate that the address has been received by the part, and goes low again to indicate that data has been written or read. cs sdi sclk sdo clke=0 0 r/ w 000 00 1d0d1d2d5 d3 d6 d4 d7 d0 d1 d2 d5 d3 d6 d4 d7 address/command byte data input/output figure 12. serial read/write format (spol = 0)
cs61880 34 ds450pp2 13.4 register set the register set available during host mode opera- tions are presented in table 10 . while the upper three bits of the parallel address are don?t cares on the cs61880, they should be set to zero for proper operation. table 10. host mode register set registers bits addr name type 7 6 5 4 3 2 1 0 00h revision/idcode r idcode refer to device id register (idr) on page 47 01h analog loopback r/w albk 7 albk 6 albk 5 albk 4 albk 3 albk 2 albk 1 albk 0 02h remote loopback r/w rlbk 7 rlbk 6 rlbk 5 rlbk 4 rlbk 3 rlbk 2 rlbk 1 rlbk 0 03h taos enable r/w taoe 7 taoe 6 taoe 5 taoe 4 taoe 3 taoe 2 taoe 1 taoe 0 04h los status r loss 7 loss 6 loss 5 loss 4 loss 3 loss 2 loss 1 loss 0 05h dfm status r dfms 7 dfms 6 dfms 5 dfms 4 dfms 3 dfms 2 dfms 1 dfms 0 06h los interrupt enable r/w lose 7 lose 6 lose 5 lose 4 lose 3 lose 2 lose 1 lose 0 07h dfm interrupt enable r/w dfme 7 dfme 6 dfme 5 dfme 4 dfme 3 dfme 2 dfme 1 dfme 0 08h los interrupt status r losi 7 losi 6 losi 5 losi 4 losi 3 losi 2 losi 1 losi 0 09h dfm interrupt status r dfmi 7 dfmi 6 dfmi 5 dfmi 4 dfmi 3 dfmi 2 dfmi 1 dfmi 0 0ah software reset r/w sres 7 sres 6 sres 5 sres 4 sres 3 sres 2 sres 1 sres 0 0bh performance monitor r/w rsvd rsvd rsvd rsvd a3 a2 a1 a0 0ch digital loopback r/w dlbk 7 dlbk 6 dlbk 5 dlbk 4 dlbk 3 dlbk 2 dlbk 1 dlbk 0 0dh los/ais mode enable r/w lame 7 lame 6 lame 5 lame 4 lame 3 lame 2 lame 1 lame 0 0eh automatic taos r/w atao 7 atao 6 atao 5 atao 4 atao 3 atao 2 atao 1 atao 0 0fh global control r/w ai raisen rsvd coden fifo jacf jasel [1:0] 10h line length channel id r/w rsvd rsvd rsvd rsvd rsvd channel id 11h line length data r/w rsvd rsvd rsvd in_ex len[3:0] 12h output disable r/w oenb 7 oenb 6 oenb 5 oenb 4 oenb 3 oenb 2 oenb 1 oenb 0 13h ais status r aiss 7 aiss 6 aiss 5 aiss 4 aiss 3 aiss 2 aiss 1 aiss 0 14h ais interrupt enable r/w aise 7 aise 6 aise 5 aise 4 aise 3 aise 2 aise 1 aise 0 15h ais interrupt status r aisi 7 aisi 6 aisi 5 aisi 4 aisi 3 aisi 2 aisi 1 aisi 0 16h awg broadcast r/w awgb 7 awgb 6 awgb 5 awgb 4 awgb 3 awgb 2 awgb 1 awgb 0 17h awg phase address r/w channel address [2:0] phase address [4:0] 18h awg phase data r/w rsvd sample data[6:0] 19h awg enable r/w awgn 7 awgn 6 awgn 5 awgn 4 awgn 3 awgn 2 awgn 1 awgn 0 1ah awg overflow interrupt enable r/w awge 7 awge 6 awge 5 awge 4 awge 3 awge 2 awge 1 awge 0 1bh awg overflow interrupt status r awgi 7 awgi 6 awgi 5 awgi 4 awgi 3 awgi 2 awgi 1 awgi 0 1ch reserved r/w rsvd 7 rsvd 6 rsvd 5 rsvd 4 rsvd 3 rsvd 2 rsvd 1 rsvd 0 1dh reserved r rsvd 7 rsvd 6 rsvd 5 rsvd 4 rsvd 3 rsvd 2 rsvd 1 rsvd 0 1eh bits clock enable r/w bits 7 bits 6 bits 5 bits 4 bits 3 bits 2 bits 1 bits 0 1fh reserved r/w rsvd 7 rsvd 6 rsvd 5 rsvd 4 rsvd 3 rsvd 2 rsvd 1 rsvd 0
cs61880 ds450pp2 35 14. register descriptions 14.1 revision/idcode register (00h) 14.2 analog loopback register (01h) 14.3 remote loopback register (02h) 14.4 taos enable register (03h) 14.5 los status register (04h) 14.6 dfm status register (05h) bit name description [7:4] revi 7-4 bits [7:4] are taken from the least-significant nibble of the device idcode, which are 0000. (refer to device id register (idr) (see section 16.3 on page 47). [3:0] revi 3-0 bits [3:0] are the revision bits from the jtag idcode register, cs61880 revision a = 0000. these bits are subject to change with the revision of the device (refer to device id register (idr) (see section 16.3 on page 47). bit name description [7:0] albk 7-0 enables analog loopbacks. a ?1? in bit n enables the loopback for channel n. refer to analog loopback (see section 12.2 on page 29) for a complete explanation. register bits default to 00h after power-up or reset. bit name description [7:0] rlbk 7-0 enables remote loopbacks. a ?1? in bit n enables the loopback for channel n. refer to host mode (see section 13 on page 32) for a complete explanation. register bits default to 00h after power-up or reset. bit name description [7:0] taoe 7-0 a ?1? in bit n of this register turns on the taos generator in channel n. register bits default to 00h after power-up or reset. bit name description [7:0] loss 7-0 register bit n is read as ?1? when los is detected on channel n. register bits default to 00h after power-up or reset. bit name description [7:0] dfms 7-0 driver failure monitor. the dfm will set bit n to ?1? when it detects a short circuit in channel n. register bits default to 00h after power-up or reset.
cs61880 36 ds450pp2 14.7 los interrupt enable register (06h) 14.8 dfm interrupt enable register (07h) 14.9 los interrupt status register (08h) 14.10 dfm interrupt status register (09h) 14.11 software reset register (0ah) 14.12 performance monitor register (0bh) 14.13 digital loopback reset register (0ch) bit name description [7:0] lose 7-0 any change in a los status register will cause the int pin to go low if corresponding bit in this register is set to ?1?. register bits default to 00h after power-up or reset. bit name description [7:0] dfme 7-0 enables interrupts for failures detected by the dfm. any change in a dfm status register bit will cause an interrupt if the corresponding bit is set to ?1? in this register. register bits default to 00h after power-up or reset. bit name description [7:0] losi 7-0 bit n of this register is set to ?1? to indicate a status change in bit n of the los status regis- ter. the bits in this register indicate a change in status since the last cleared los interrupt. register bits default to 00h after power-up or reset. bit name description [7:0] dfmi 7-0 bit n of this register is set to ?1? to indicate a status change in bit n of the dfm status regis- ter. the bits in this register indicate a change in status since the last cleared dfm interrupt. register bits default to 00h after power-up or reset. bit name description [7:0] sres 7-0 writing to this register initializes all registers to their default settings. register bits default to 00h after power-up or reset. bit name description [7:4] rsvd 7-4 reserved (these bits must be set to 0.) [3:0] a[3:0] the g.772 monitor is directed to a given channel based on the state of the four least signifi- cant bits of this register. register bits default to 00h after power-up or reset. the follow- ing table shows the settings needed to select a specific channel?s receiver or transmitter to perform g.772 monitoring. see table 6 on page 22 for g.772 monitor settings. bit name description [7:0] dlbk 7-0 setting register bit n to ?1? enables the digital loopback for channel n. refer to digital loop- back (see section 12.3 on page 30) for a complete explanation. register bits default to 00h after power-up or reset.
cs61880 ds450pp2 37 14.14 los/ais mode enable register (0dh) 14.15 automatic taos register (0eh) 14.16 global control register (0fh) bit name description [7:0] lame 7-0 setting bit n to ?1? enables etsi 300 233 compliant los/ais for channel n; setting bit n to ?0? enables itu g.775 compliant los/ais for channel n. register bits default to 00h after power-up or reset. bit name description [7:0] atao 7-0 setting bit n to ?1? enables automatic taos generation on channel n when los is detected. register bits default to 00h after power-up or reset. bit name description this register is the global control for the awg auto-increment, automatic ais insertion, encoding/decoding and the jitter attenuators location, fifo length and corner frequency for all eight channels. register bits default to 00h after power-up or reset. [7] awg auto- increment the awg auto-increment bit indicates whether to auto-increment the awg phase address register (17h) (see section 14.24 on page 39) after each access. thus, when this bit is set, the phase samples address portion of the address register increments after each read or write access. this bit must be set before any bit in the awg enable register is set, if this function is required. [6] raisen on los, this bit controls the automatic ais insertion into all eight receiver paths. 0 = disabled 1 = enabled [5] rsvd reserved (this bit must be set to 0.) [4] coden line encoding/decoding selection 0 = hdb3 1 = ami [3] fifo length jitter attenuator fifo length selection 0 = 32 bits 1 = 64 bits [2] jacf jitter attenuator corner frequency selection 0 = 1.25hz 1 = 2.50hz [1:0] jasel [1:0] these bits select the position of the jitter attenuator. table 11. jitter attenuator position selection jasel 1 jasel 0 position 00 disabled 0 1 transmit path 10 disabled 1 1 receive path
cs61880 38 ds450pp2 14.17 line length channel id register (10h) 14.18 line length data register (11h) 14.19 output disable register (12h) 14.20 ais status register (13h) bit name description [7:3] rsvd 7-3 reserved (these bits must be set to 0.) [2:0] llid 2-0 the value written to these bits specify the liu channel for which the pulse shape configura- tion data (register 11h) applies. for example, writing a value of a binary 000 to the 3-lsbs will select channel 0. the pulse shape configuration data for the channel specified in this reg- ister are written or read through the line length data register (11h). register bits default to 00h after power-up or reset. bit name description the value written to the 4-lsbs of this register specifies whether the device is operating in either e1 75 ? or e1 120 ? mode and the associated pulse shape as shown below is being transmitted. register bits default to 00h after power-up or reset. [7:5] rsvd reserved (these bits must be set to 0.) [4] int_extb this bit specifies the use of internal (int_extb = 1) or external (int_extb = 0) receiver line matching. the line impedance for both the receiver and transmitter are chosen through the len [3:0] bits in this register. [3:0] len[3:0] these bits set the line impedance for both the receiver and the transmitter path and the desired pulse shape for a specific channel. the channel is selected with the line length channel id register (0x10). the following table shows the available transmitter pulse shapes. bit name description [7:0] oenb 7-0 setting bit n of this register to ?1? high-z the tx output driver on channel n of the device. register bits default to 00h after power-up or reset. bit name description [7:0] aiss 7-0 a ?1? in bit position n indicates that the receiver has detected an ais condition on channel n, which generates an interrupt on the int pin. register bits default to 00h after power-up or reset. table 12. transmitter pulse shape selection len [3:0] operation mode line length selection phase samples per ui 0000 e1 120 ? 3.0 v 12 1000 e1 75 ? 2.37 v 12
cs61880 ds450pp2 39 14.21 ais interrupt enable register (14h) 14.22 ais interrupt status register (15h) 14.23 awg broadcast register (16h) 14.24 awg phase address register (17h) 14.25 awg phase data register (18h) bit name description [7:0] aise 7-0 this register enables changes in the ais status register to be reflected in the ais interrupt status register, thus causing an interrupt on the int pin. register bits default to 00h after power-up or reset. bit name description [7:0] aisi 7-0 bit n is set to ?1? to indicate a change of status of bit n in the ais status register. the bits in this register indicate which channel changed in status since the last cleared ais interrupt. register bits default to 00h after power-up or reset. bit name description [7:0] awgb 7-0 setting bit n to ?1? causes the phase data in the awg phase data register to be written to the corresponding channel or channels simultaneously. (refer to arbitrary waveform gen- erator (see section 15 on page 42). register bits default to 00h after power-up or reset. bit name description [7:5] awga these bits specify the target channel 0-7. (refer to arbitrary waveform generator (see section 15 on page 42). register bits default to 00h after power-up or reset. [4:0] pa[4:0] these bits specify 1 of 24 phase sample address locations of the awg, that the phase data in the awg phase data register is written to or read from. register bits default to 00h after power-up or reset. bit name description [7] rsvd reserved (this bit must be set to 0.) [6:0] awgd [6:0] these bits are used for the pulse shape data that will be written to or read from the awg phase location specified by the awg phase address register. the value written to or read from this register will be written to or read from the awg phase sample location specified by the awg phase address register. a software reset through the software reset register does not effect the contents of this register. the data in each phase is a 7-bit 2?s complement number (the maximum positive value is 3fh and the maximum negative value is 40h). (refer to arbitrary waveform generator (see section 15 on page 42). register bits default to 00h after power-up.
cs61880 40 ds450pp2 14.26 awg enable register (19h) 14.27 awg overflow interrupt enable register (1ah) 14.28 awg overflow interrupt status register (1bh) 14.29 reserved register (1ch) 14.30 reserved register (1dh) 14.31 bits clock enable register (1eh) 14.32 reserved register (1fh) bit name description [7:0] awgn 7-0 the awg enable register is used for selecting the source of the customized transmission pulse-shape. setting bit n to ?1? in this register selects the awg as the source of the output pulse shape for channel n. when bit n is set to ?0? the pre-programmed pulse shape in the rom is selected for transmission on channel n. (refer to arbitrary waveform generator (see section 15 on page 42). register bits default to 00h after power-up or reset. bit name description [7:0] awge 7-0 this register enables changes in the overflow status to be reflected in the awg interrupt sta- tus register, thus causing as interrupt on the int pin. interrupts are maskable on a per-chan- nel basis. register bits default to 00h after power-up or reset. bit name description [7:0] awgi 7-0 the bits in this register indicate a change in status since the last awg overflow interrupt. an awg overflow occurs when invalid phase data are entered, such that a sample-by-sample addition of ui0 and ui1 results in values that exceed the arithmetic range of the 7-bit repre- sentation. reading this register clears the interrupt, which deactivates the int pin. register bits default to 00h after power-up or reset. bit name description [7:0] rsvd 7-0 reserved bit name description [7:0] rsvd 7-0 reserved bit name description [7:0] bits 7-0 writing a ?1? to bit n in this register changes channel n to a stand-alone timing recovery unit used for g.703 clock recovery. (refer to building integrated timing systems (bits) clock mode (see section 8 on page 23) for a better description of the g.703 clock recovery function). register bits default to 00h after power-up or reset. bit name description [7:0] rsvd 7-0 reserved
cs61880 ds450pp2 41 14.33 status registers the following status registers are read-only: los status register (04h) (see section 14.5 on page 35), dfm status register (05h) (see sec- tion 14.6 on page 35) and ais status register (13h) (see section 14.20 on page 38). the cs61880 generates an interrupt on the int pin any time an unmasked status register bit changes. 14.33.1 interrupt enable registers the interrupt enable registers: los interrupt en- able register (06h) (see section 14.7 on page 36), dfm interrupt enable register (07h) (see sec- tion 14.8 on page 36), ais interrupt enable reg- ister (14h) (see section 14.21 on page 39) and awg overflow interrupt enable register (1ah) (see section 14.27 on page 40) , enable changes in status register state to cause an interrupt on the int pin. interrupts are maskable on a per channel basis. when an interrupt enable register bit is 0, the corresponding status register bit is dis- abled from causing an interrupt on the int pin. note: disabling an interrupt has no effect on the sta- tus reflected in the associated status register. 14.33.2 interrupt status registers the following interrupt status registers: los in- terrupt status register (08h) (see section 14.9 on page 36), dfm interrupt status register (09h) (see section 14.10 on page 36), ais inter- rupt status register (15h) (see section 14.22 on page 39) and awg overflow interrupt status register (1bh) (see section 14.28 on page 40) , in- dicate a change in status of the corresponding status registers in host mode. reading these registers clears the interrupt, which deactivates the int pin.
cs61880 42 ds450pp2 15. arbitrary waveform generator using the arbitrary waveform generator (awg) allows the user to customize the transmit pulse shapes to compensate for nonstandard cables, transformers, protection circuitry, or to reduce power consumption by reducing the output pulse amplitude. a channel is configured for a custom pulse shape by enabling the awg for that channel and then storing data representing the pulse shape into the 24 phase sample locations. each channel has a separate awg, so all eight channels can have a different customized pulse shape. the micropro- cessor interface, is used to read from or write to the awg, while the device is in host mode. in the awg ram, the pulse shape is divided into two unit intervals (ui). there are 12 phase sample addresses in each ui. the first ui is for the main part of the pulse and the second ui is for the ?tail? of the pulse (refer to figure 13 ). a complete pulse- shape is represented by 24 phase samples. data written in the first ui represents a valid pulse shape, while data in the second ui must be set to zero at all times. writing values other that zero to the second ui will cause the pulse shape to be in- valid. the data in each phase sample is a 7-bit two?s com- plement number with a maximum positive value of 0x3f, and a maximum negative value of 0x40. the terms ?positive? and ?negative? are defined for a positive going pulse only. the pulse generation cir- cuitry automatically inverts the pulse for negative going pulses. the data stored in the lowest phase address corresponds to the first phase sample that will be transmitted in time. the typical voltage step for each mode of operation is as follows: for e1 75 ? mode the typical voltage step is 42mv/lsb and for e1 120 ? mode the typical voltage step is 54mv/lsb all voltage steps are measured across the transformer secondary. the following procedure describes how to enable and write data into the awg ram to produce cus- tomized pulse shapes to be transmitted for a specif- ic channel or channels. first, enable the awg function for a specific channel or channels by writ- ing a ?1? to the corresponding bits in the awg en- able register (19h) (see section 14.26 on page 40). when the corresponding bit or bits in the awg enable register are set to ?0? pre-pro- grammed pulse shapes are selected for transmis- sion. then the desired channel and phase sample address must be written to the awg phase ad- dress register (17h) (see section 14.24 on page 39). once the channel and phase sample ad- dress have been written, the actual phase sample data may be entered into the awg phase data register (18h) (see section 14.25 on page 39) at the selected phase sample address selected by the lower five bits of the awg phase address regis- ter (17h) (see section 14.24 on page 39)). to change the phase sample address of the selected channel the user may use either of the following steps. the user can re-write the phase sample ad- dress to the awg phase address register or set the auto-increment bit (bit 7) in the global control register (0fh) (see section 14.16 on page 37) to ?1? before writing to the awg phase data regis- ter. when this bit is set to ?1? only the first phase e1 awg example u1 u2 figure 13. arbitrary waveform ui
cs61880 ds450pp2 43 sample address (00000 binary) needs to be written to the awg phase address register (17h) (see section 14.24 on page 39), and each subsequent ac- cess (read or write) to the awg phase data reg- ister (18h) (see section 14.25 on page 39) will automatically increment the phase sample address. the channel address, however, remains unaffected by the auto-increment mode. the awg phase address register (17h) (see section 14.24 on page 39) needs to be re-written in order to re-start the phase sample address sequence from the new phase sample address. the awg broadcast function allows the same data to be written to multiple channels simultaneously. this is done with the use of the awg broadcast register (16h) (see section 14.23 on page 39), each bit in the awg broadcast register corre- sponds to a different channel (e.g. bit 0 is channel 0, and bit 3 is channel 3 and etc.). to use the awg broadcast function mclk must be present. when mclk is inactive the awg broadcast function is disabled. to write the same pulse shaping data to multiple channels, simple set the corresponding bit to ?1? in the awg broadcast register (16h) (see section 14.23 on page 39) before accessing the awg phase data register. this function only requires that one of the eight channel addresses be written to the awg phase address register (17h) (see section 14.24 on page 39). during an awg read sequence, the bits in the awg broadcast register are ig- nored. during an awg write sequence, the select- ed channel or channels are specified by both the channel address specified by the upper bits of the awg phase address register (17h) (see section 14.24 on page 39) and the selected channel or chan- nels in the awg broadcast register (16h) (see section 14.23 on page 39). during a multiple channel write the first channel that is written to, is the channel that was addressed by the awg phase address register. this chan- nel?s bit in the awg broadcast register can be set to either ?1? or ?0?. for a more descriptive explanation of how to use the awg function refer to the application note an204, how to use the cs61880/cs61884 arbi- trary waveform generator . 16. jtag support the cs61880 supports the ieee boundary scan specification as described in the ieee 1149.1 stan- dards. a test access port (tap) is provided that consists of the tap controller, the instruction reg- ister (ir), by-pass register (bpr), device id regis- ter (idr), the boundary scan register (bsr), and the 5 standard pins (trst , tck, tms, tdi, and tdo). a block diagram of the test access port is shown in figure 14 on page 44 . the test clock in- put (tck) is used to sample input data on tdi, and shift output data through tdo. the tms input is used to step the tap controller through its various states. the instruction register is used to select test execu- tion or register access. the by-pass register pro- vides a direct connection between the tdi input and the tdo output. the device identification reg- ister contains a 32-bit device identifier. the boundary scan register is used to support test- ing of ic inter-connectivity. using the boundary scan register, the digital input pins can be sampled and shifted out on tdo. in addition, this register can also be used to drive digital output pins to a user defined state.
cs61880 44 ds450pp2 16.1 tap controller the tap controller is a 16 state synchronous state machine clocked by the rising edge of tck. the tms input governs state transitions as shown in figure 15 . the value shown next to each state tran- sition in the diagram is the value that must be on tms when it is sampled by the rising edge of tck. 16.1.1 jtag reset trst resets all jtag circuitry. 16.1.2 test-logic-reset the test-logic-reset state is used to disable the test logic when the part is in normal mode of operation. this state is entered by asynchronously asserting trst or forcing tms high for 5 tck periods. 16.1.3 run-test-idle the run-test-idle state is used to run tests. 16.1.4 select-dr-scan this is a temporary controller state. 16.1.5 capture-dr in this state, the boundary scan register captures input pin data if the current instruction is extest or sample/preload. 16.1.6 shift-dr in this controller state, the active test data register connected between tdi and tdo, as determined by the current instruction, shifts data out on tdo on each rising edge of tck. 16.1.7 exit1-dr this is a temporary state. the test data register se- lected by the current instruction retains its previous value. parallel latched output boundary scan data register device id data register bypass data register instruction (shift) register tap controller parallel latched output tdi tck digital output pins digital input pins jtag block mux tdo tms figure 14. test access port architecture
cs61880 ds450pp2 45 16.1.8 pause-dr the pause state allows the test controller to tempo- rarily halt the shifting of data through the current test data register. 16.1.9 exit2-dr this is a temporary state. the test data register se- lected by the current instruction retains its previous value. 16.1.10 update-dr the boundary scan register is provided with a latched parallel output to prevent changes while data is shifted in response to the extest and sample/preload instructions. when the tap controller is in this state and the boundary scan register is selected, data is latched into the parallel output of this register from the shift-register path on the falling edge of tck. the data held at the latched parallel output changes only in this state. 16.1.11 select-ir-scan this is a temporary controller state. the test data register selected by the current instruction retains its previous state. 16.1.12 capture-ir in this controller state, the instruction register is loaded with a fixed value of ?01? on the rising edge of tck. this supports fault-isolation of the board- level serial test data path. 16.1.13 shift-ir in this state, the shift register contained in the in- struction register is connected between tdi and tdo and shifts data one stage towards its serial output on each rising edge of tck. 1 0 test-logic-reset run-test/idle select-dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select- i r-scan capture- ir shift- ir exit1- ir pause- ir exit2- ir update- ir 0 11 1 1 1 11 1 1 1 11 1 1 0 0 0 0 0 0 0 0 00 0 0 0 1 0 figure 15. tap controller state diagram
cs61880 46 ds450pp2 16.1.14 exit1-ir this is a temporary state. the test data register se- lected by the current instruction retains its previous value. 16.1.15 pause-ir the pause state allows the test controller to tempo- rarily halt the shifting of data through the instruc- tion register. 16.1.16 exit2-ir this is a temporary state. the test data register se- lected by the current instruction retains its previous value. 16.1.17 update-ir the instruction shifted into the instruction register is latched into the parallel output from the shift-reg- ister path on the falling edge of tck. when the new instruction has been latched, it becomes the current instruction. the test data registers selected by the current instruction retain their previous val- ue. 16.2 instruction register (ir) the 3-bit instruction register selects the test to be performed and/or the data register to be accessed. the valid instructions are shifted in lsb first and are listed in table 13 : 16.2.1 extest the extest instruction allows testing of off-chip circuitry and board-level interconnect. extest connects the bsr to the tdi and tdo pins. 16.2.2 sample/preload the sample/preload instruction samples all device inputs and outputs. this instruction places the bsr between the tdi and tdo pins. the bsr is loaded with samples of the i/o pins by the cap- ture-dr state. 16.2.3 idcode the idcode instruction connects the device iden- tification register to the tdo pin. the device iden- tification code can then be shifted out tdo using the shift-dr state. 16.2.4 bypass the bypass instruction connects a one tck de- lay register between tdi and tdo. the instruction is used to bypass the device. table 13. jtag instructions ir code instruction 000 extest 100 sample/preload 110 idcode 111 bypass
cs61880 ds450pp2 47 16.3 device id register (idr) revision section: 0h = rev a, 1h = rev b and so on. the device identification code [27 - 12] is derived from the last three digits of the part number (880). the lsb is a constant 1, as defined by ieee 1149.1. 17. boundary scan register (bsr) the bsr is a shift register that provides access to the digital i/o pins. the bsr is used to read and write the device pins to verify interchip connectivity. each pin has a corresponding scan cell in the register. the pin to scan cell mapping is given in the boundary scan register description shown in table 14 . note: data is shifted lsb first into the bsr register. cs61880 idcode register(idr) revision device idcode register manufacturer code 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 109876543210 0h 0h 8h 8h 0h 0h 0h 9h 0000000010001000000000 0011001001 table 14. boundary scan register bsr bit pin name cell type bit symbol 0 los7 o los7 1 rneg7 o rneg7 2 rpos7 o rpos7 3 rclk7 o rclk7 4 - note 2 hiz7_b 5 tneg7 i tneg7 6 tpos7 i tpos7 7 tclk7 i tclk7 8 los6 o los6_b 9 rneg6 o rneg6 10 rpos6 o rpos6 11 rclk6 o rclk6 12 - note 2 hiz6_b 13 tneg6 i tneg6 14 tpos6 i tpos6 15 tclk6 i tclk6 16 mclk i mclk 17 mode i mode_tri 18 mode i mode_in 19 addr4 i addr4 20 addr3 i addr3 21 addr2 i addr2 22 addr1 i addr1 23 addr0 i addr0 24 loop0/d0 i lpt0 25 loop0/d0 i lpi0 26 loop0/d0 o lpo0 27 loop1/d1 i lpt1
cs61880 48 ds450pp2 28 loop1/d1 i lpi1 29 loop1/d1 o lpo1 30 loop2/d2 i lpt2 31 loop2/d2 i lpi2 32 loop2/d2 o lpo2 33 loop3/d3 i lpt3 34 loop3/d3 i lpi3 35 loop3/d3 o lpo3 36 loop4/d4 i lpt4 37 loop4/d4 i lpi4 38 loop4/d4 o lpo4 39 loop5/d5 i lpt5 40 loop5/d5 i lpi5 41 loop5/d5 o lpo5 42 loop6/d6 i lpt6 43 loop6/d6 i lpi6 44 loop6/d6 o lpo6 45 loop7/d7 i lpt7 46 loop7/d7 i lpi7 47 loop7/d7 o lpo7 48 - note 1 lpoen 49 tclk1 i tclk1 50 tpos1 i tpos1 51 tneg1 i tneg1 52 rclk1 o rclk1 53 rpos1 o rpos1 54 rneg1 o rneg1 55 - note 2 hiz1_b 56 los1 o los1 57 tclk0 i tclk0 58 tpos0 i tpos0 59 tneg0 i tneg0 60 rclk0 o rclk0 61 rpos0 o rpos0 62 rneg0 o rneg0 63 - note 2 hiz0_b 64 los0 o los0 65 mux i mux 66 los3 o los3 67 rneg3 o rneg3 68 rpos3 o rpos3 69 rclk3 o rclk3 70 - note 2 hiz3_b 71 tneg3 i tneg3 72 tpos3 i tpos3 table 14. boundary scan register (continued) bsr bit pin name cell type bit symbol
cs61880 ds450pp2 49 notes: 1) lpoen controls the loop[7:0] pins. setting lpoen to ?1? configures loop[7:0] as outputs. the output value driven on the pins are determined by the values written to lpo[7:0]. setting lpoen to ?0? high-z all the pins. in this mode, the input values driven to these loop[7:0] can be read via lpi[7:0]. 2) hiz_b controls the rposx, rnegx, and rclkx pins. when hiz_b is high, the outputs are enabled; when hiz_b is low, the outputs are placed in a high impedance state (high-z). 3) rdyoen controls the ack_b pin. setting rdyoen to ?1? enables output on ack_b. setting acken to ?0? high -z the ack_b pin. 73 tclk3 i tclk3 74 los2 o los2 75 rneg2 o rneg2 76 rpos2 o rpos2 77 rclk2 o rclk2 78 - note 2 hiz2_b 79 tneg2 i tneg2 80 tpos2 i tpos2 81 tclk2 i tclk2 82 int_b o int_b 83 rdy o rdyout 84 - note 3 rdyoen 85 wr_b i wr_b 86 rd_b i rd_b 87 ale i ale 88 cs_b i cs_b 89 cs_b i cs_b_tri 90 intl i intl 91 cblsel i cblsel_tri 92 cblsel i cblsel_in 93 tclk5 i tclk5 94 tpos5 i tpos5 95 tneg5 i tneg5 96 rclk5 o rclk5 97 rpos5 o rpos5 98 rneg5 o rneg5 99 - note 2 hiz5_b 100 los5 o los5 101 tclk4 i tclk4 102 tpos4 i tpos4 103 tneg4 i tneg4 104 rclk4 o rclk4 105 rpos4 o rpos4 106 rneg4 o rneg4 107 - note 2 hiz4_b 108 los4 o los4 109 txoe i txoe 110 clke i clke table 14. boundary scan register (continued) bsr bit pin name cell type bit symbol
cs61880 50 ds450pp2 18. applications figure 16. internal rx/tx impedance matching + rgnd +3.3v rv+ t1 1:2 ref cs61880 one channel tring ttip transmit line t2 1:1.15 rtip rring r1 r2 13.3k ? gnd cblsel tv+ vccio +3.3v + tgnd + gndio nc 75 ? cable 120 ? cable +3.3v 68 f 0.1 f 0.1 f 0.1 f 0.1 f receive line note 2 note 1 note 1 notes:1) required capacitor between each tv+, rv+, vccio and tgnd, rgnd, gndio respec- tively. 2) common decoupling capacitor for all tvcc and tgnd pins. component e1 75 ? coaxial cable e1 120 ? twisted pair cable r1 ( ? ) 15 15 r2 ( ? ) 15 15
cs61880 ds450pp2 51 figure 17. internal tx, external rx impedance matching + rgnd 0.1 f +3.3v rv+ t1 1:2 ref tring ttip t2 1:1.15 rtip rring r1 r2 13.3k ? gnd cblsel tv+ vccio +3.3v + tgnd + 0.1 f gndio nc 75 ? cable 120 ? cable gnd 1k ? 1k ? transmit line receive line 0.1 f 0.1 f note 1 note 1 note 2 68 f cs61880 one channel notes: 1)required capacitor between each tv+, rv+, vccio and tgnd, rgnd, gndio respectively. 2)common decoupling capacitor for all tvcc and tgnd pins. component e1 75 ? coaxial cable e1 120 ? twisted pair cable r1 ( ? ) 9.31 15 r2 ( ? ) 9.31 15
cs61880 52 ds450pp2 18.1 transformer specifications recommended transformer specifications are shown in table 15 . any transformer used with the cs61880 should meet or exceed these specifica- tions. 18.2 crystal oscillator specifications when a reference clock signal is not available, a cmos crystal oscillator may be used as the refer- ence clock signal. the oscillator must have a mini- mum symmetry of 40-60% and minimum stability of + 100ppm. 18.3 line protection secondary protection components can be added to the line interface circuitry to provide lightning surge and ac power-cross immunity. for addition- al information on the different electrical safety standards and specific applications circuit recom- mendations, refer to application note an034, sec- ondary line protection for t1 and e1 cards . table 15. transformer specifications descriptions specifications turns ratio receive 1:2 turns ratio transmit 1:1.15 primary inductance 1.5mh min. @ 1024 khz primary leakage induc- tance 0.3 h max @ 1024 khz secondary leakage induc- tance 0.4 h max @ 1024 khz inter winding capacitance 18 pf max, primary to secondary et-constant 16v - s min.
cs61880 ds450pp2 53 19. characteristics and specifications 19.1 absolute maximum ratings caution: operations at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. 19.2 recommended operating conditions notes: 1. human body model 2. transient current of up to 100 ma will not cause scr latch-up. also ttip, tring, tv+ and tgnd can withstand a continuous current of 100 ma. 3. power consumption while driving line load over the full operating temperature and power supply voltage range. includes all ic channels and loads. digital inputs are within 10% of the supply rails and digital outputs are driving a 50 pf capacitive load. 4. typical consumption corresponds to 50% ones density for at 3.3 v. 5. maximum consumption corresponds to 100% ones density at 3.465 v. 6. this specification guarantees ttl compatibility (v oh = 2.4 v @ i out = -400 a). 7. output drivers are ttl compatible. 8. pulse amplitude measured at the output of the transformer across a 75 ? load. 9. pulse amplitude measured at the output of the transformer across a 120 ? load. parameter symbol min. max units dc supply (referenced to rgnd = tgnd = 0v) rv+ tv+ - - 4.0 4.0 v v dc supply vccio -0.5 4.6 v input voltage, any digital pin except cblsel, mode and loop(n) pins (referenced to gndio = 0v) v ih gndio -0.5 5.3 v input voltage cblsel, mode & loop(n) pins (referenced to gndio = 0v) v ih gndio -0.5 vccio +0.5 v input voltage, rtip and rring pins tgnd -0.5 tv+ +0.5 v esd voltage, any pin note 1 2k - v input current, any pin note 2 i ih -10 +10 ma maximum power dissipation, in package p p -1.73w ambient operating temperature t a -40 85 c storage temperature t stg -65 150 c parameter symbol min. typ max units dc supply rv+, tv+ 3.135 3.3 3.465 v dc supply vccio 3.135 3.3 3.465 v ambient operating temperature t a -40 25 85 c power consumption, e1 mode, 75 ? line load notes 3 , 4 , 5 - - 660 1040 mw power consumption, e1 mode, 120 ? line load notes 3 , 4 , 5 - -640950mw
cs61880 54 ds450pp2 19.3 digital characteristics (ta = -40 c to 85 c; tv+, rv+ = 3.3 v 5%; gnd = 0 v) 19.4 transmitter analog characteristics (ta = -40 c to 85 c; tv+, rv+ = 3.3 v 5%; gnd = 0 v) parameter symbol min. typ max units high-level input voltage note 6 v ih 2.0 - - v low-level input voltage note 6 v il --0.8v loop[7:0] low-level input voltage v ihl - - 1/3 vccio-0.2 v loop[7:0] mid-level input voltage v ihm 1/3 vccio +0.2 1/2 vccio 2/3 vccio-0.2 v loop[7:0] high-level input voltage v ihh 2/3 vccio +0.2 - - v high-level output voltage notes 6 , 7 i out = -400 a v oh 2.4 - - v low-level output voltage notes 6 , 7 i out = 1.6 ma v ol --0.4v input leakage current -10 - + 10 a input leakage for loop pins -150 +150 a parameter min. typ max units output pulse amplitudes e1 75 ? notes 8 , 9 , 11 e1 120 ? 2.14 2.7 2.37 3.0 2.6 3.3 v v ratio of positive to negative pulses notes 8 , 9 , 11 amplitude at center of pulse interval width at 50% of nominal amplitude 0.95 0.95 - - 1.05 1.05 pulse amplitude of a space e1 120 ? e1 75 ? -0.3 -0.237 - - 0.3 0.237 v v transmit return loss 51 khz to 102 khz 102 kh to 2048 khz notes 10 , 11 , 12 2048 khz to 3072 khz -14 -14 -14 -20 -19 -18 - - - db jitter added by the transmitter 10 hz - 8 khz 8khz - 40khz notes 10 , 13 10 hz - 40 khz broad band - - - - 0.010 0.009 0.007 0.015 0.020 0.025 0.025 0.050 ui transmitter short circuit current per channel - - 50 ma rms
cs61880 ds450pp2 55 19.5 receiver analog characteristics (ta = -40 c to 85 c; tv+, rv+ = 3.3 v 5%; gnd = 0 v)) notes: 10. parameters guaranteed by design and characterization. 11. using components on the cdb61880 evaluation board in internal match impedance mode. 12. return loss = 20log10 abs((z1 + z0) / (z1 - z0)) where z1 - impedance of the transmitter or receiver, and z0 = cable impedance. 13. assuming that jitter free clock is input to tclk. 14. jitter tolerance for 6 db input signal levels. jitter tolerance increases at lower frequencies. hdb3 coders enabled. 15. in data recovery mode. 16. jitter attenuator in the receive path. parameter min. typ max units allowable cable attenuation @ 1024khz and 772khz - - - 12 db rtip/rring input impedance e1 120 ? load (internal line matching mode) e1 75 ? load note 10 - - 13k 50 - - ? rtip/rring input impedance e1 120 ? load (external line matching mode) e1 75 ? load note 10 - - 13k 13k - - ? receiver dynamic range 0.5 - - vp signal to noise margin (per g.703, o151 @ 6db cable atten). - -18 - db receiver squelch level 150 mv los threshold - 200 - mv los hysteresis 50 mv data decision threshold note 10 42 50 58 % of peak input jitter tolerance 1 hz - 1.8 hz notes 10 , 14 , 16 20 hz - 2.4 khz 18 khz - 100 khz 18 1.5 0.2 - - - - - - ui input return loss 51 khz - 102 khz 102 khz - 2048 khz notes 10 , 11 , 12 2048 khz - 3072 khz -18 -18 -18 -28 -30 -27 - - - db
cs61880 56 ds450pp2 19.6 jitter attenuator characteristics (ta = -40 c to 85 c; tv+, rv+ = 3.3 v 5%; gnd = 0 v) notes: 17. attenuation measured with sinusoidal input filter equal to 3/4 of measured jitter tolerance. circuit attenuates jitter at 20 db/decade above the corner frequency. output jitter can increase significantly when more than 28 ui?s are input to the attenuator. 18. measurement is not effected by the position of the jitter attenuator. parameter min. typ max units jitter attenuator corner frequency note 10 , 18 (depends on jacf bit in host mode) - - 1.25 2.50 - - hz e1 jitter attenuation 3 hz to 40 hz note 10 , 17 400 hz to 100 khz + 0.5 -19.5 - - - - db attenuator input jitter tolerance before fifo 32-bit fifo over flow and under flow note 10 64-bit fifo - - 24 56 - - ui ui delay through jitter attenuator only 32-bit fifo note 10 64-bit fifo - - 16 32 - - ui ui intrinsic jitter in remote loopback notes 10 , 16 --0.11ui 110 100 1k 10k 0 attenuation in db frequency in hz + 0.5 2 57 1.4k 20 400 40 + 10 - 10 - 20 - 30 - 50 - 40 - 60 - 19.5 - 6 - 70 100k itu g.736 typ. e1 @ 1.25 hz cf typ. e1 @ 2.5 hz cf figure 18. jitter transfer characteristic vs. g.736 & tbr 12/13
cs61880 ds450pp2 57 peak to peak jitter (ui) frequency in hz 110 1k 100 100k 1.8 4.9 20 300 10k 2.4k 18k 1 .1 10 100 .2 .4 1.5 1000 18 28 138 300 itu g.823 typ. e1 performance figure 19. jitter tolerance characteristic vs. g.823
cs61880 58 ds450pp2 19.7 master clock switching characteristics 19.8 transmit switching characteristics 19.9 receive switching characteristics notes: 19. output load capacitance = 50pf. 20. mclk is not active. parameter symbol min. typ max units master clock (mclk) master clock frequency mclk 2.048 mhz master clock tolerance - -100 +100 ppm master clock duty cycle - 40 50 60 % parameter symbol min. typ max units tclk frequency 1/t pw2 -2.048- mhz tpos/tneg pulse width (rz mode) 236 244 252 ns tclk tolerance (nrz mode) -50 - 50 ppm tclk duty cycle t pwh2 /t pw2 --90% tclk pulse width 20 - - ns tclk burst rate note 10 --20mhz tpos/tneg to tclk falling setup time (nrz mode) t su2 25 - - ns tclk falling to tpos/tneg hold time (nrz mode) t h2 25 - - ns txoe asserted low to tx driver high-z - - 1 s tclk held low to driver high-z note 20 81220 s parameter symbol min. typ max units rclk duty cycle note 10 40 50 60 % rclk pulse width note 10 196 244 328 ns rpos/rneg pulse width (rz mode) note 10 200 244 300 ns rpos/rneg to rclk rising setup time note 10 t su 200 244 ns rpos/rneg to rclk hold time note 10 t h 200 244 ns rpos/rneg output to rclk output (rz mode) note 10 --5ns rise/fall time, rpos, rneg, rclk, los outputs note 19 t r , t f --85ns
cs61880 ds450pp2 59 rclk t su rpos/rneg clke = 1 t su t h t h rpos/rneg clke = 0 figure 20. recovered clock and data switching characteristics tpos/tneg tclk t pw2 t pwh2 t su2 t h2 figure 21. transmit clock and data switching characteristics any digital output 10% 90% t r t f 10% 90% figure 22. signal rise and fall characteristics
cs61880 60 ds450pp2 19.10 switching characteristics - serial port notes: 21. if spol = 0, then cs should return high no sooner than 20 ns after the 16 th rising edge of sclk during a serial port read. parameter symbol min. typ. max unit sdi to sclk setup time t dc -20-ns sclk to sdi hold time t cdh -20-ns sclk low time t cl -50-ns sclk high time t ch -50-ns sclk rise and fall time t r , t f -15-ns cs to sclk setup time t cc -20-ns sclk to cs hold time note 21 t cch -20-ns cs inactive time t cwh -70-ns sdo valid to sclk note 21 t cdv -60-ns cs to sdo high z t cdz -50-ns cs sdi sclk sdo clke=1 last addr bit sdo clke=0 high z t cdv t cdv t cdz d0 d1 d0 d6 d1 d6 d7 d7 figure 23. serial port read timing diagram cs sclk t cc sdi lsb lsb msb t ch t cl t cch t cwh t dc t cdh t cdh figure 24. serial port write timing diagram
cs61880 ds450pp2 61 19.11 switching characteristics - parallel port (multiplexed mode) parameter ref. # min. typ. max unit pulse width as or ale high 1 25 - - ns muxed address setup time to as or ale low 2 10 - - ns muxed address hold time 3 5 - - ns delay time as or ale to wr , rd or ds 45--ns cs & r/w setup time before wr , rd or ds low 5 0 - - ns cs & r/w hold time 6 0 - - ns pulse width, wr , rd , or ds 770- -ns write data setup time 8 30 - - ns write data hold time 9 30 - - ns output data delay time from rd or ds low 10 - - 70 ns read data hold time 11 5 - - ns delay time wr , rd , or ds to ale or as rise 12 30 - - ns wr or rd low to rdy low 13 - - 20 ns wr or rd low to rdy high 14 - - 70 ns wr or rd high to rdy high-z 15 - - 40 ns ds low to ack high 16 - - 20 ns ds low to ack low 17 - - 70 ns ds high to ack high-z 18 - - 40 ns
cs61880 62 ds450pp2 ale wr d[7:0] rdy high-z high-z cs 1 12 4 7 6 9 8 3 5 2 13 15 14 address write data figure 25. parallel port timing - write; intel multiplexed address / data bus mode ale rd d[7:0] rdy high-z high-z cs 1 12 4 7 6 3 5 2 13 15 14 11 10 address read data figure 27. parallel mode port timing - read; intel multiplexed address / data bus mode
cs61880 ds450pp2 63 d[7:0] r/w ds as write data high-z high-z address 1 5 2 4 3 16 17 18 7 6 cs 8 12 9 ack figure 26. parallel port timing - write; motorola multiplexed address / data bus mode d[7:0] r/w ds as read data high-z high-z address 1 5 2 4 3 16 17 18 7 6 cs 10 12 11 ack figure 28. parallel port timing - read; motorola multiplexed address / data bus mode
cs61880 64 ds450pp2 19.12 switching characteristics- parallel port (non-multiplexed mode) parameter ref. # min. typ. max unit address setup time to wr , rd or ds low 1 10 - - ns address hold time 2 5 - - ns cs & r/w setup time before wr , rd or ds low 3 0 - - ns cs & r/w hold time 4 0 - - ns pulse width, wr , rd , or ds 570- -ns write data setup time 6 30 - - ns write data hold time 7 30 - - ns output data delay time from rd or ds 8--70ns read data hold time 9 5 - - ns wr or rd low to rdy low 10 - - 20 ns wr , rd or ds low to rdy high 11 - - 70 ns wr , rd or ds high to rdy high-z 12 - - 40 ns ds low to ack high 13 - - 20 ns ds low to ack low 14 - - 70 ns ds high to ack high-z 15 - - 40 ns
cs61880 ds450pp2 65 a[4:0] d[7:0] ale rdy rd (pulled high) cs high-z 1 9 10 high-z 11 12 2 5 3 4 8 address read data figure 29. parallel port timing - read; intel non-multiplexed address / data bus mode a[4:0] d[7:0] ale rdy wr (pulled high) cs high-z 1 7 10 high-z 11 12 2 5 3 4 6 address write data figure 30. parallel port timing - write; intel non-multiplexed address / data bus mode
cs61880 66 ds450pp2 a[4:0] d[7:0] cs (pulled high) ds high-z 1 9 high-z 14 15 2 5 3 4 8 address read data as ack r/w 13 figure 31. parallel port timing - read; motorola non-multiplexed address / data bus mode (pulled high) high-z 1 7 13 high-z 14 15 2 5 3 4 6 address write data ack d[7:0] cs r/w ds as a[4:0] figure 32. parallel port timing - write; motorola non-multiplexed address / data bus mode
cs61880 ds450pp2 67 19.13 switching characteristics - jtag parameter symbol min. max units cycle time t cyc 200 - ns tms/tdi to tck rising setup time t su 50 - ns tck rising to tms/tdi hold time t h 50 - ns tck falling to tdo valid t dv -70ns tck tms tdi tdo t su t h t cyc t dv figure 33. jtag switching characteristics
cs61880 68 ds450pp2 20. compliant recommendations and specifications etsi ets 300-011 etsi ets 300-166 etsi ets 300-233 etsi tbr 12/13 ieee 1149.1 itu-t i.431 itu-t g.703 itu-t g.704 itu-t g.706 itu-t g.732 itu-t g.735 itu-t g.736 itu-t g.742 itu-t g.772 itu-t g.775 itu-t g.783 itu-t g.823 itu-t o.151 oftel otr-001
cs61880 ds450pp2 69 21. 160-ball fbga package dimensions figure 34. 160-ball fbga package drawing
cs61880 70 ds450pp2 22. 144-pin lqfp package dimensions table 16. 144-pin package dimensions inches millimeters dim min nom max min nom max a --- 0.55 0.063 --- 1.40 1.60 a1 0.002 0.004 0.006 0.05 0.10 0.15 b 0.007 0.008 0.011 0.17 0.20 0.27 d 0.854 0.866 bsc 0.878 21.70 22.0 bsc 22.30 d1 0.783 0.787 bsc 0.791 19.90 20.0 bsc 20.10 e 0.854 0.866 bsc 0.878 21.70 22.0 bsc 22.30 e1 0.783 0.787 bsc 0.791 19.90 20.0 bsc 20.10 e* 0.016 0.020 0.024 0.40 0.50 bsc 0.60 0.000 4 7.000 0.00 4 7.00 l 0.018 0.024 0.030 0.45 0.60 0.75 * nominal pin pitch is 0.50 mm controlling dimension is mm. jedec designation: ms022 e1 e d1 d 1 e l b a1 a figure 35. 144-pin lqfp package drawing

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